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» DVM Test Report: LL_Nominal|F_Low|Disabled|80% Load|BodePlot

Test Details
Schematic DVM -- PFC_CCM_sync_DLL.sxsch
Test LL_Nominal|F_Low|Disabled|80% Load|BodePlot
Date / Time 22/03/2022 07:37
Report Directory DVM_REPORTS\2022-03-22-06_18\LL_Nominal\F_Low\Disabled\80% Load\BodePlot
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 96.446953%
gain_crossover_freq 10.184492
gain_margin 29.384346
ILOAD
AVG
200.04693m
MIN
199.12137m
MAX
200.98275m
RMS
200.04799m
PK2PK
1.8613819m
ISRC
AVG
-186.67489p
MIN
-994.38933m
MAX
994.38933m
RMS
690.74996m
PK2PK
1.9887787
min_phase 20.880963
min_phase_freq 57.546639
phase_crossover_freq 88.372678
phase_margin 57.749992
Power(LOAD) 80.038395
Power(SRC) 82.986961
VLOAD
AVG
400.09386
MIN
398.24274
MAX
401.9655
RMS
400.09598
PK2PK
3.7227638
VSRC
AVG
-297.0842p
MIN
-169.99978
MAX
169.99978
RMS
120.208
PK2PK
339.99957
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (401.966) is less than or equal to Max. Output1 Voltage Spec (420)
Min_VLOAD PASS: Min. Output1 Voltage (398.243) is greater than or equal to Min. Output1 Voltage Spec (380)
min_gain_margin PASS: Gain Margin (29.3843) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (57.75) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac56_4954.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop9_4866.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop9_4855.sxgph
Other SXGPH Files
Output#pop simplis_pop9_4753.sxgph
Vdc-Vdrain#pop simplis_pop9_4764.sxgph
SIGNAL#pop simplis_pop9_4780.sxgph
Samples#pop simplis_pop9_4791.sxgph
COMP#pop simplis_pop9_4812.sxgph
triggers#pop simplis_pop9_4833.sxgph
VL#pop simplis_pop9_4844.sxgph
Load_offset#pop simplis_pop9_4898.sxgph