» SIMPLIS DVM Test Report Overview

General
Schematic DVM -- PFC_CCM_sync_DLL.sxsch
Testplan dvm_advanced.testplan
Original Testplan Filename POP on AC-DC CCM PFC.testplan
Date / Time 2022-03-22 06:18
Report Directory DVM_REPORTS\2022-03-22-06_18
Log File dvm_advanced.log
# of Tests Run 4 of 4 (All Pass)
Total Time 1h 19m 36s
Design Specifications
Circuit Name Critical Conduction Mode PFC
Description with prototype PFC POP trigger
Input 1 (Low Line) 120.2082 VRMS Nominal (100 VRMS to 155.563 VRMS)
Input 1 (High Line) 220 VRMS Nominal (170 VRMS to 265 VRMS)
Output 1 400 V (±5%) @ 250m A
Low Frequency 50Hz
High Frequency 60Hz
Switching Frequency 400kHz
Excel-compatible Results
Scalar Results dvm_advanced_table_scalars.txt
Spec Results dvm_advanced_table_specs.txt
Statistic Results dvm_advanced_table_statistics.txt
Statistic Specs dvm_advanced_table_statspecs.txt
Test 1 of 4top ▲
Test Label LL_Nominal|F_Low|Disabled|100% Load|FindACSteadyState
Simulator simplis
Test Report LL_Nominal\F_Low\Disabled\100% Load\FindACSteadyState\report.txt.html
Status PASS
Test Time 22m 11s
Test 2 of 4top ▲
Test Label LL_Nominal|F_Low|Disabled|100% Load|BodePlot
Simulator simplis
Test Report LL_Nominal\F_Low\Disabled\100% Load\BodePlot\report.txt.html
Status PASS
Test Time 21m 36s
Test 3 of 4top ▲
Test Label LL_Nominal|F_Low|Disabled|80% Load|FindACSteadyState
Simulator simplis
Test Report LL_Nominal\F_Low\Disabled\80% Load\FindACSteadyState\report.txt.html
Status PASS
Test Time 26m 0s
Test 4 of 4top ▲
Test Label LL_Nominal|F_Low|Disabled|80% Load|BodePlot
Simulator simplis
Test Report LL_Nominal\F_Low\Disabled\80% Load\BodePlot\report.txt.html
Status PASS
Test Time 9m 43s