
- What Slows SIMPLIS Down? (2)
- Large Number of Piecewise Linear Topologies
- Avoid unnecessary PWL topologies
- Minimize use of switches for logic functions
- Use minimum number of PWL segments on PWL devices consistent with achieving required accuracy (2.1.SyncBuck_4phase.sxsch)
Always be clear about the simulation objective of every simulation
Only include the modeling complexity needed to obtain the required accuracy