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» DVM Test Report: Efficiency and Loop Characterization|Vin Maximum|15% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Maximum|15% Load
Date / Time 12/10/2015 6:10 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\15% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.8319%
eta_max 95.8319%
Frequency(CLK) 98.9508k
gain_crossover_freq 1.4611k
gain_margin 31.578
gmargin_max 31.578
gxover_max 1.4611k
ILOAD
AVG
753.551m
MIN
753.312m
MAX
753.762m
RMS
753.551m
PK2PK
449.912u
iload_max 753.551m
ISRC
AVG
47.3846m
MIN
-483.689m
MAX
527.599m
RMS
239.087m
PK2PK
1.01129
min_phase 113.289
min_phase_freq 1.4611k
phase_crossover_freq 44.4389k
phase_margin 113.23
pmargin_max 113.23
Power(LOAD) 18.1584
Power(SRC) 18.9481
sw_freq_max 98.9508k
VLOAD
AVG
24.0971
MIN
24.0896
MAX
24.1037
RMS
24.0971
PK2PK
14.0701m
VSRC
AVG
399.995
MIN
399.947
MAX
400.048
RMS
399.995
PK2PK
101.129m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.1037) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0896) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (31.578) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (113.23) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac17_1014.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop17_980.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop17_970.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop17_961.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop17_975.sxgph
Other SXGPH Files
default#1003#pop simplis_pop17_1003.sxgph
Modulator#pop simplis_pop17_1008.sxgph