Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Maximum|20% Load |
Date / Time | 12/10/2015 6:11 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\20% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.9535% |
eta_max | 95.9535% |
Frequency(CLK) | 98.1026k |
gain_crossover_freq | 2.48014k |
gain_margin | 30.7982 |
gmargin_max | 30.7982 |
gxover_max | 2.48014k |
ILOAD | AVG 1.00456 MIN 1.00413 MAX 1.00489 RMS 1.00456 PK2PK 753.224u |
iload_max | 1.00456 |
ISRC | AVG 63.0854m MIN -490.028m MAX 564.476m RMS 256.702m PK2PK 1.0545 |
min_phase | 101.21 |
min_phase_freq | 2.48014k |
phase_crossover_freq | 42.6554k |
phase_margin | 101.168 |
pmargin_max | 101.168 |
Power(LOAD) | 24.2067 |
Power(SRC) | 25.2276 |
sw_freq_max | 98.1026k |
VLOAD | AVG 24.097 MIN 24.087 MAX 24.1048 RMS 24.097 PK2PK 17.764m |
VSRC | AVG 399.994 MIN 399.944 MAX 400.049 RMS 399.994 PK2PK 105.45m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1048) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.087) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (30.7982) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (101.168) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac18_1074.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop18_1040.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop18_1030.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop18_1021.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
|
SXGPH File | simplis_pop18_1035.sxgph |
Other SXGPH Files | |
default#1063#pop | simplis_pop18_1063.sxgph |
Modulator#pop | simplis_pop18_1068.sxgph |