| Test Details | |
| Schematic | 8.2_LLC Closed Loop.sxsch | 
| Test | Efficiency and Loop Characterization|Vin Maximum|30% Load | 
| Date / Time | 12/10/2015 6:11 PM | 
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\30% Load | 
| Log File | report.txt | 
| Screenshot | schematic.png | 
| Status | PASS | 
| Simulator | simplis | 
| Deck | input.deck | 
| Init | input.deck.init | 
| Measured Scalar Values | |
| Efficiency | 96.0216% | 
| eta_max | 96.0216% | 
| Frequency(CLK) | 97.0418k | 
| gain_crossover_freq | 3.67299k | 
| gain_margin | 29.3715 | 
| gmargin_max | 29.3715 | 
| gxover_max | 3.67299k | 
| ILOAD | AVG 1.50655 MIN 1.50561 MAX 1.50718 RMS 1.50655 PK2PK 1.56179m  | 
				
| iload_max | 1.50655 | 
| ISRC | AVG 94.5385m MIN -521.862m MAX 614.054m RMS 289.793m PK2PK 1.13592  | 
				
| min_phase | 83.5981 | 
| min_phase_freq | 3.67299k | 
| phase_crossover_freq | 38.9898k | 
| phase_margin | 83.3771 | 
| pmargin_max | 83.3771 | 
| Power(LOAD) | 36.3029 | 
| Power(SRC) | 37.807 | 
| sw_freq_max | 97.0418k | 
| VLOAD | AVG 24.0967 MIN 24.0818 MAX 24.1065 RMS 24.0967 PK2PK 24.7555m  | 
				
| VSRC | AVG 399.991 MIN 399.939 MAX 400.052 RMS 399.991 PK2PK 113.592m  | 
				
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1065) is less than or equal to Max. Output1 Voltage Spec (25.2) | 
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0818) is greater than or equal to Min. Output1 Voltage Spec (22.8) | 
| min_gain_margin | PASS: Gain Margin (29.3715) is greater than Min. Gain Margin (12) | 
| min_phase_margin | PASS: Phase Margin (83.3771) is greater than Min. Phase Margin (35) | 
						![]() Bode Plot 
								GAIN 
								PHASE 
							 | 
				|
| SXGPH File | simplis_ac20_1194.sxgph | 
						![]() LOAD 
								VLOAD 
								ILOAD 
							 | 
				|
| SXGPH File | simplis_pop20_1160.sxgph | 
						![]() SRC 
								VSRC 
								ISRC 
							 | 
				|
| SXGPH File | simplis_pop20_1150.sxgph | 
						![]() Primary 
								IDQ1 
								IDQ2 
								Im 
								Ip 
								Ir 
								VSW 
							 | 
				|
| SXGPH File | simplis_pop20_1141.sxgph | 
						![]() Secondary 
								CLK 
								ICout 
								Is1 
								Is2 
								Vs 
							 | 
				|
| SXGPH File | simplis_pop20_1155.sxgph | 
| Other SXGPH Files | |
| default#1183#pop | simplis_pop20_1183.sxgph | 
| Modulator#pop | simplis_pop20_1188.sxgph |