| Test Details | |
| Schematic | 8.2_LLC Closed Loop.sxsch | 
| Test | Efficiency and Loop Characterization|Vin Maximum|40% Load | 
| Date / Time | 12/10/2015 6:12 PM | 
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\40% Load | 
| Log File | report.txt | 
| Screenshot | schematic.png | 
| Status | PASS | 
| Simulator | simplis | 
| Deck | input.deck | 
| Init | input.deck.init | 
| Measured Scalar Values | |
| Efficiency | 95.9703% | 
| eta_max | 95.9703% | 
| Frequency(CLK) | 96.1755k | 
| gain_crossover_freq | 4.08126k | 
| gain_margin | 27.691 | 
| gmargin_max | 27.691 | 
| gxover_max | 4.08126k | 
| ILOAD | AVG 2.00852 MIN 2.00686 MAX 2.00953 RMS 2.00852 PK2PK 2.67078m  | 
				
| iload_max | 2.00852 | 
| ISRC | AVG 126.101m MIN -561.607m MAX 667.721m RMS 326.135m PK2PK 1.22933  | 
				
| min_phase | 78.0679 | 
| min_phase_freq | 4.08126k | 
| phase_crossover_freq | 34.9413k | 
| phase_margin | 77.9294 | 
| pmargin_max | 77.9294 | 
| Power(LOAD) | 48.3978 | 
| Power(SRC) | 50.43 | 
| sw_freq_max | 96.1755k | 
| VLOAD | AVG 24.0962 MIN 24.0763 MAX 24.1082 RMS 24.0962 PK2PK 31.8274m  | 
				
| VSRC | AVG 399.987 MIN 399.933 MAX 400.056 RMS 399.987 PK2PK 122.933m  | 
				
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1082) is less than or equal to Max. Output1 Voltage Spec (25.2) | 
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0763) is greater than or equal to Min. Output1 Voltage Spec (22.8) | 
| min_gain_margin | PASS: Gain Margin (27.691) is greater than Min. Gain Margin (12) | 
| min_phase_margin | PASS: Phase Margin (77.9294) is greater than Min. Phase Margin (35) | 
						![]() Bode Plot 
								GAIN 
								PHASE 
							 | 
				|
| SXGPH File | simplis_ac22_1314.sxgph | 
						![]() LOAD 
								VLOAD 
								ILOAD 
							 | 
				|
| SXGPH File | simplis_pop22_1280.sxgph | 
						![]() SRC 
								VSRC 
								ISRC 
							 | 
				|
| SXGPH File | simplis_pop22_1270.sxgph | 
						![]() Primary 
								IDQ1 
								IDQ2 
								Im 
								Ip 
								Ir 
								VSW 
							 | 
				|
| SXGPH File | simplis_pop22_1261.sxgph | 
						![]() Secondary 
								CLK 
								ICout 
								Is1 
								Is2 
								Vs 
							 | 
				|
| SXGPH File | simplis_pop22_1275.sxgph | 
| Other SXGPH Files | |
| default#1303#pop | simplis_pop22_1303.sxgph | 
| Modulator#pop | simplis_pop22_1308.sxgph |