Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Maximum|50% Load |
Date / Time | 12/10/2015 6:12 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\50% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.8651% |
eta_max | 95.8651% |
Frequency(CLK) | 95.4094k |
gain_crossover_freq | 4.44166k |
gain_margin | 26.0284 |
gmargin_max | 26.0284 |
gxover_max | 4.44166k |
ILOAD | AVG 2.51046 MIN 2.50786 MAX 2.51194 RMS 2.51046 PK2PK 4.08416m |
iload_max | 2.51046 |
ISRC | AVG 157.784m MIN -598.26m MAX 739.219m RMS 365.569m PK2PK 1.33748 |
min_phase | 73.1077 |
min_phase_freq | 4.44166k |
phase_crossover_freq | 31.5046k |
phase_margin | 72.8871 |
pmargin_max | 72.8871 |
Power(LOAD) | 60.491 |
Power(SRC) | 63.1002 |
sw_freq_max | 95.4094k |
VLOAD | AVG 24.0956 MIN 24.0707 MAX 24.1097 RMS 24.0956 PK2PK 38.9922m |
VSRC | AVG 399.984 MIN 399.926 MAX 400.06 RMS 399.984 PK2PK 133.748m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1097) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.0707) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (26.0284) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (72.8871) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac23_1374.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop23_1340.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop23_1330.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop23_1321.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
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SXGPH File | simplis_pop23_1335.sxgph |
Other SXGPH Files | |
default#1363#pop | simplis_pop23_1363.sxgph |
Modulator#pop | simplis_pop23_1368.sxgph |