Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Maximum|90% Load |
Date / Time | 12/10/2015 6:13 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\90% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.3670% |
eta_max | 95.3670% |
Frequency(CLK) | 93.1495k |
gain_crossover_freq | 5.68428k |
gain_margin | 19.6796 |
gmargin_max | 19.6796 |
gxover_max | 5.68428k |
ILOAD | AVG 4.51775 MIN 4.50933 MAX 4.52217 RMS 4.51775 PK2PK 12.8414m |
iload_max | 4.51775 |
ISRC | AVG 285.397m MIN -727.201m MAX 1.0681 RMS 541.408m PK2PK 1.7953 |
min_phase | 53.6011 |
min_phase_freq | 5.68428k |
phase_crossover_freq | 22.0815k |
phase_margin | 53.2556 |
pmargin_max | 53.2556 |
Power(LOAD) | 108.842 |
Power(SRC) | 114.129 |
sw_freq_max | 93.1495k |
VLOAD | AVG 24.092 MIN 24.0472 MAX 24.1155 RMS 24.092 PK2PK 68.2811m |
VSRC | AVG 399.971 MIN 399.893 MAX 400.073 RMS 399.971 PK2PK 179.53m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1155) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.0472) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (19.6796) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (53.2556) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac27_1614.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop27_1580.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop27_1570.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop27_1561.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
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SXGPH File | simplis_pop27_1575.sxgph |
Other SXGPH Files | |
default#1603#pop | simplis_pop27_1603.sxgph |
Modulator#pop | simplis_pop27_1608.sxgph |