back to overview ▲

» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|25% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Minimum|25% Load
Date / Time 12/10/2015 6:14 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\25% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.7316%
eta_min 95.7316%
Frequency(CLK) 80.0052k
gain_crossover_freq 4.84903k
gain_margin 26.1537
gmargin_min 26.1537
gxover_min 4.84903k
ILOAD
AVG
1.25549
MIN
1.25483
MAX
1.25613
RMS
1.25549
PK2PK
1.30442m
iload_min 1.25549
ISRC
AVG
87.8099m
MIN
-579.526m
MAX
599.715m
RMS
307.797m
PK2PK
1.17924
min_phase 44.7731
min_phase_freq 4.84903k
phase_crossover_freq 31.4433k
phase_margin 44.5241
pmargin_min 44.5241
Power(LOAD) 30.2532
Power(SRC) 31.6021
sw_freq_min 80.0052k
VLOAD
AVG
24.0968
MIN
24.0843
MAX
24.109
RMS
24.0968
PK2PK
24.7032m
VSRC
AVG
359.991
MIN
359.94
MAX
360.058
RMS
359.991
PK2PK
117.924m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.109) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0843) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (26.1537) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (44.5241) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac33_1974.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop33_1940.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop33_1930.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop33_1921.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop33_1935.sxgph
Other SXGPH Files
default#1963#pop simplis_pop33_1963.sxgph
Modulator#pop simplis_pop33_1968.sxgph