Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Minimum|50% Load |
Date / Time | 12/10/2015 6:15 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\50% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.7087% |
eta_min | 95.7087% |
Frequency(CLK) | 79.2935k |
gain_crossover_freq | 4.73587k |
gain_margin | 23.3309 |
gmargin_min | 23.3309 |
gxover_min | 4.73587k |
ILOAD | AVG 2.5099 MIN 2.50727 MAX 2.51192 RMS 2.5099 PK2PK 4.6436m |
iload_min | 2.5099 |
ISRC | AVG 175.531m MIN -567.682m MAX 767.712m RMS 385.656m PK2PK 1.33539 |
min_phase | 48.4238 |
min_phase_freq | 4.73587k |
phase_crossover_freq | 23.6863k |
phase_margin | 48.2373 |
pmargin_min | 48.2373 |
Power(LOAD) | 60.4653 |
Power(SRC) | 63.1764 |
sw_freq_min | 79.2935k |
VLOAD | AVG 24.0907 MIN 24.0657 MAX 24.11 RMS 24.0908 PK2PK 44.2884m |
VSRC | AVG 359.982 MIN 359.923 MAX 360.057 RMS 359.982 PK2PK 133.539m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.11) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.0657) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (23.3309) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (48.2373) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac37_2214.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop37_2180.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop37_2170.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop37_2161.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
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SXGPH File | simplis_pop37_2175.sxgph |
Other SXGPH Files | |
default#2203#pop | simplis_pop37_2203.sxgph |
Modulator#pop | simplis_pop37_2208.sxgph |