Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Minimum|60% Load |
Date / Time | 12/10/2015 6:15 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\60% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.5993% |
eta_min | 95.5993% |
Frequency(CLK) | 79.0558k |
gain_crossover_freq | 4.7144k |
gain_margin | 21.3369 |
gmargin_min | 21.3369 |
gxover_min | 4.7144k |
ILOAD | AVG 3.0109 MIN 3.00713 MAX 3.01373 RMS 3.0109 PK2PK 6.5985m |
iload_min | 3.0109 |
ISRC | AVG 210.749m MIN -562.435m MAX 852.619m RMS 425.053m PK2PK 1.41505 |
min_phase | 47.882 |
min_phase_freq | 4.7144k |
phase_crossover_freq | 20.1384k |
phase_margin | 47.718 |
pmargin_min | 47.718 |
Power(LOAD) | 72.5135 |
Power(SRC) | 75.8515 |
sw_freq_min | 79.0558k |
VLOAD | AVG 24.0837 MIN 24.0536 MAX 24.1062 RMS 24.0837 PK2PK 52.5227m |
VSRC | AVG 359.979 MIN 359.915 MAX 360.056 RMS 359.979 PK2PK 141.505m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1062) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.0536) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (21.3369) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (47.718) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac38_2274.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop38_2240.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop38_2230.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop38_2221.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
|
SXGPH File | simplis_pop38_2235.sxgph |
Other SXGPH Files | |
default#2263#pop | simplis_pop38_2263.sxgph |
Modulator#pop | simplis_pop38_2268.sxgph |