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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|15% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Nominal|15% Load
Date / Time 12/10/2015 6:07 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\15% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.6316%
eta_nom 95.6316%
Frequency(CLK) 88.3639k
gain_crossover_freq 3.39574k
gain_margin 28.0994
gmargin_nom 28.0994
gxover_nom 3.39574k
ILOAD
AVG
753.507m
MIN
753.266m
MAX
753.756m
RMS
753.507m
PK2PK
489.301u
iload_nom 753.507m
ISRC
AVG
49.9824m
MIN
-532.351m
MAX
554.207m
RMS
259.162m
PK2PK
1.08656
min_phase 84.9521
min_phase_freq 3.39574k
phase_crossover_freq 35.2226k
phase_margin 84.9241
pmargin_nom 84.9241
Power(LOAD) 18.1572
Power(SRC) 18.9866
sw_freq_nom 88.3639k
VLOAD
AVG
24.0969
MIN
24.0894
MAX
24.1047
RMS
24.0969
PK2PK
15.3049m
VSRC
AVG
379.995
MIN
379.945
MAX
380.053
RMS
379.995
PK2PK
108.656m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.1047) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0894) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (28.0994) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (84.9241) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac3_174.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop3_140.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop3_130.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop3_121.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop3_135.sxgph
Other SXGPH Files
default#163#pop simplis_pop3_163.sxgph
Modulator#pop simplis_pop3_168.sxgph