| Test Details | |
| Schematic | 8.2_LLC Closed Loop.sxsch | 
| Test | Efficiency and Loop Characterization|Vin Nominal|20% Load | 
| Date / Time | 12/10/2015 6:07 PM | 
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\20% Load | 
| Log File | report.txt | 
| Screenshot | schematic.png | 
| Status | PASS | 
| Simulator | simplis | 
| Deck | input.deck | 
| Init | input.deck.init | 
| Measured Scalar Values | |
| Efficiency | 95.7872% | 
| eta_nom | 95.7872% | 
| Frequency(CLK) | 87.9671k | 
| gain_crossover_freq | 4.28593k | 
| gain_margin | 27.6259 | 
| gmargin_nom | 27.6259 | 
| gxover_nom | 4.28593k | 
| ILOAD | AVG 1.00451 MIN 1.00409 MAX 1.00491 RMS 1.00451 PK2PK 813.823u  | 
				
| iload_nom | 1.00451 | 
| ISRC | AVG 66.5208m MIN -537.044m MAX 556.78m RMS 275.851m PK2PK 1.09382  | 
				
| min_phase | 64.4503 | 
| min_phase_freq | 4.28593k | 
| phase_crossover_freq | 34.1001k | 
| phase_margin | 64.1252 | 
| pmargin_nom | 64.1252 | 
| Power(LOAD) | 24.2057 | 
| Power(SRC) | 25.2703 | 
| sw_freq_nom | 87.9671k | 
| VLOAD | AVG 24.0969 MIN 24.087 MAX 24.1062 RMS 24.0969 PK2PK 19.1988m  | 
				
| VSRC | AVG 379.993 MIN 379.944 MAX 380.054 RMS 379.993 PK2PK 109.382m  | 
				
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1062) is less than or equal to Max. Output1 Voltage Spec (25.2) | 
| Min_VLOAD | PASS: Min. Output1 Voltage (24.087) is greater than or equal to Min. Output1 Voltage Spec (22.8) | 
| min_gain_margin | PASS: Gain Margin (27.6259) is greater than Min. Gain Margin (12) | 
| min_phase_margin | PASS: Phase Margin (64.1252) is greater than Min. Phase Margin (35) | 
						![]() Bode Plot 
								GAIN 
								PHASE 
							 | 
				|
| SXGPH File | simplis_ac4_234.sxgph | 
						![]() LOAD 
								VLOAD 
								ILOAD 
							 | 
				|
| SXGPH File | simplis_pop4_200.sxgph | 
						![]() SRC 
								ISRC 
								VSRC 
							 | 
				|
| SXGPH File | simplis_pop4_190.sxgph | 
						![]() Primary 
								IDQ1 
								IDQ2 
								Im 
								Ip 
								Ir 
								VSW 
							 | 
				|
| SXGPH File | simplis_pop4_181.sxgph | 
						![]() Secondary 
								CLK 
								ICout 
								Is1 
								Is2 
								Vs 
							 | 
				|
| SXGPH File | simplis_pop4_195.sxgph | 
| Other SXGPH Files | |
| default#223#pop | simplis_pop4_223.sxgph | 
| Modulator#pop | simplis_pop4_228.sxgph |