Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Nominal|35% Load |
Date / Time | 12/10/2015 6:08 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\35% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.9151% |
eta_nom | 95.9151% |
Frequency(CLK) | 87.3265k |
gain_crossover_freq | 4.78929k |
gain_margin | 26.3038 |
gmargin_nom | 26.3038 |
gxover_nom | 4.78929k |
ILOAD | AVG 1.75754 MIN 1.75626 MAX 1.75847 RMS 1.75754 PK2PK 2.21408m |
iload_nom | 1.75754 |
ISRC | AVG 116.224m MIN -538.365m MAX 644.276m RMS 321.679m PK2PK 1.18264 |
min_phase | 48.0547 |
min_phase_freq | 4.78929k |
phase_crossover_freq | 30.8916k |
phase_margin | 47.8355 |
pmargin_nom | 47.8355 |
Power(LOAD) | 42.3512 |
Power(SRC) | 44.1549 |
sw_freq_nom | 87.3265k |
VLOAD | AVG 24.0969 MIN 24.0795 MAX 24.1096 RMS 24.0969 PK2PK 30.073m |
VSRC | AVG 379.988 MIN 379.936 MAX 380.054 RMS 379.988 PK2PK 118.264m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1096) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.0795) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (26.3038) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (47.8355) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac7_414.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop7_380.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop7_370.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop7_361.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
|
SXGPH File | simplis_pop7_375.sxgph |
Other SXGPH Files | |
Modulator#pop | simplis_pop7_408.sxgph |
default#403#pop | simplis_pop7_403.sxgph |