Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Nominal|40% Load |
Date / Time | 12/10/2015 6:08 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\40% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.8953% |
eta_nom | 95.8953% |
Frequency(CLK) | 87.151k |
gain_crossover_freq | 4.81162k |
gain_margin | 25.4461 |
gmargin_nom | 25.4461 |
gxover_nom | 4.81162k |
ILOAD | AVG 2.00855 MIN 2.00688 MAX 2.00971 RMS 2.00855 PK2PK 2.83394m |
iload_nom | 2.00855 |
ISRC | AVG 132.85m MIN -536.492m MAX 676.374m RMS 338.212m PK2PK 1.21287 |
min_phase | 47.1751 |
min_phase_freq | 4.81162k |
phase_crossover_freq | 28.8776k |
phase_margin | 46.9325 |
pmargin_nom | 46.9325 |
Power(LOAD) | 48.3997 |
Power(SRC) | 50.4714 |
sw_freq_nom | 87.151k |
VLOAD | AVG 24.0969 MIN 24.077 MAX 24.1107 RMS 24.0969 PK2PK 33.7239m |
VSRC | AVG 379.987 MIN 379.932 MAX 380.054 RMS 379.987 PK2PK 121.287m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1107) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.077) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (25.4461) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (46.9325) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac8_474.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop8_440.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop8_430.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop8_421.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
|
SXGPH File | simplis_pop8_435.sxgph |
Other SXGPH Files | |
default#463#pop | simplis_pop8_463.sxgph |
Modulator#pop | simplis_pop8_468.sxgph |