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» DVM Test Report: Steady-State|Steady-State|Vin Minimum|10%

Test Details
Schematic 4.2_LTC3406B - DVM ADVANCED.sxsch
Test Steady-State|Steady-State|Vin Minimum|10%
Date / Time 12/10/2015 5:46 PM
Report Directory run_blt_in_and_prmt_grphs\Steady-State\Steady-State\VinMinimum\10%
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 91.1347%
Efficiency_Min 91.1347%
Frequency(CLK) 955.678k
ILOAD
AVG
150.066m
MIN
149.751m
MAX
150.331m
RMS
150.066m
PK2PK
579.894u
ISRC
AVG
55.097m
MIN
277.747u
MAX
450.136m
RMS
119.045m
PK2PK
449.858m
Power(LOAD) 225.943m
Power(SRC) 247.922m
VLOAD
AVG
1.50563
MIN
1.50247
MAX
1.50829
RMS
1.50563
PK2PK
5.81809m
VSRC
AVG
4.49994
MIN
4.49955
MAX
4.5
RMS
4.49994
PK2PK
449.858u
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (1.50829) is less than or equal to Max. Output1 Voltage Spec (1.58025)
Min_VLOAD PASS: Min. Output1 Voltage (1.50247) is greater than or equal to Min. Output1 Voltage Spec (1.42975)
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop24_824.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop24_814.sxgph
default
CLK
ILOUT
SW
VOUT
SXGPH File simplis_pop24_819.sxgph
Other SXGPH Files
clock#pop simplis_pop24_806.sxgph