back to overview ▲

» DVM Test Report: Steady-State|Steady-State|Vin Minimum|100%

Test Details
Schematic 4.2_LTC3406B - DVM ADVANCED.sxsch
Test Steady-State|Steady-State|Vin Minimum|100%
Date / Time 12/10/2015 5:48 PM
Report Directory run_blt_in_and_prmt_grphs\Steady-State\Steady-State\VinMinimum\100%
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 66.4168%
Efficiency_Min 66.4168%
Frequency(CLK) 929.646k
ILOAD
AVG
1.44503
MIN
1.4413
MAX
1.44867
RMS
1.44503
PK2PK
7.3662m
ISRC
AVG
701.209m
MIN
381.375u
MAX
1.72039
RMS
1.01462
PK2PK
1.72001
Power(LOAD) 2.09506
Power(SRC) 3.15441
VLOAD
AVG
1.44984
MIN
1.4461
MAX
1.45349
RMS
1.44984
PK2PK
7.39072m
VSRC
AVG
4.4993
MIN
4.49828
MAX
4.5
RMS
4.4993
PK2PK
1.72001m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (1.45349) is less than or equal to Max. Output1 Voltage Spec (1.58025)
Min_VLOAD PASS: Min. Output1 Voltage (1.4461) is greater than or equal to Min. Output1 Voltage Spec (1.42975)
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop33_1139.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop33_1129.sxgph
default
CLK
ILOUT
SW
VOUT
SXGPH File simplis_pop33_1134.sxgph
Other SXGPH Files
clock#pop simplis_pop33_1121.sxgph