back to overview ▲

» DVM Test Report: Steady-State|Steady-State|Vin Minimum|60%

Test Details
Schematic 4.2_LTC3406B - DVM ADVANCED.sxsch
Test Steady-State|Steady-State|Vin Minimum|60%
Date / Time 12/10/2015 5:47 PM
Report Directory run_blt_in_and_prmt_grphs\Steady-State\Steady-State\VinMinimum\60%
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 76.3555%
Efficiency_Min 76.3555%
Frequency(CLK) 955.646k
ILOAD
AVG
900.346m
MIN
898.198m
MAX
902.315m
RMS
900.347m
PK2PK
4.11635m
ISRC
AVG
394.593m
MIN
381.169u
MAX
1.16501
RMS
606.234m
PK2PK
1.16463
Power(LOAD) 1.35554
Power(SRC) 1.7753
VLOAD
AVG
1.50557
MIN
1.50198
MAX
1.50886
RMS
1.50557
PK2PK
6.88342m
VSRC
AVG
4.49961
MIN
4.49883
MAX
4.5
RMS
4.49961
PK2PK
1.16463m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (1.50886) is less than or equal to Max. Output1 Voltage Spec (1.58025)
Min_VLOAD PASS: Min. Output1 Voltage (1.50198) is greater than or equal to Min. Output1 Voltage Spec (1.42975)
LOAD
ILOAD
VLOAD
SXGPH File simplis_pop29_999.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop29_989.sxgph
default
CLK
ILOUT
SW
VOUT
SXGPH File simplis_pop29_994.sxgph
Other SXGPH Files
clock#pop simplis_pop29_981.sxgph