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» DVM Test Report: Steady-State|Steady-State|Vin Nominal|50%

Test Details
Schematic 4.2_LTC3406B - DVM ADVANCED.sxsch
Test Steady-State|Steady-State|Vin Nominal|50%
Date / Time 12/10/2015 5:44 PM
Report Directory run_blt_in_and_prmt_grphs\Steady-State\Steady-State\VinNominal\50%
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 79.1235%
Efficiency_nom 79.1235%
Frequency(CLK) 955.649k
ILOAD
AVG
750.315m
MIN
748.345m
MAX
751.985m
RMS
750.316m
PK2PK
3.63996m
ISRC
AVG
285.599m
MIN
423.431u
MAX
1.03248
RMS
475.287m
PK2PK
1.03206
Power(LOAD) 1.1297
Power(SRC) 1.42777
VLOAD
AVG
1.50563
MIN
1.50168
MAX
1.50898
RMS
1.50563
PK2PK
7.30416m
VSRC
AVG
4.99971
MIN
4.99897
MAX
5
RMS
4.99971
PK2PK
1.03206m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (1.50898) is less than or equal to Max. Output1 Voltage Spec (1.58025)
Min_VLOAD PASS: Min. Output1 Voltage (1.50168) is greater than or equal to Min. Output1 Voltage Spec (1.42975)
LOAD
ILOAD
VLOAD
SXGPH File simplis_pop6_194.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop6_184.sxgph
default
CLK
ILOUT
SW
VOUT
SXGPH File simplis_pop6_189.sxgph
Other SXGPH Files
clock#pop simplis_pop6_176.sxgph