Application G – Simulating the Impact of the Power Distribution Network (PDN) on Power Supply Systems with High di/dt Loads

To download the examples for the Applications Module, click Applications_Examples.zip.

In this topic:

G.1 The PDN Simulation Challenge

In high-performance microprocessor applications, the power distribution network (PDN) refers to the network of components, interconnections, and printed circuit board paths used to distribute power from a switching power supply source to the input voltage pins of the microprocessor load. The proper design of the PDN is vital to ensuring that the microprocessor load receives the correct voltage and current over all operating conditions, including during current steps on the order of 1000 A and slew rates on the order of 1 A/ns.


	Figure G.1: Critical elements of a Voltage Regulator Module include the Controller, the Power Stage, the Power Distribution Network and the discrete bulk output capacitors.

Figure G.1 illustrates the top-level schematic of the working example used in this analysis showing the Voltage Regulator Module (VRM) made up of an IC Controller and the Power Stage of a 7-phase Synchronous Buck DC-DC Converter. The 7 output inductors of the power stage are connected via the PDN to the input terminals of the microprocessor load. The bulk energy-storage output capacitors are connected in parallel at multiple points along the PCB paths between the output inductors of the power stage and the input terminals of the load.

This VRM is designed to deliver power to high current loads with very high di/dt requirements such as high-end microprocessors. Central to the converter's operation is the controller, which persistently senses fluctuations in output voltage and adjusts the duty cycle of each phase of the converter Power Stage to maintain a constant voltage at the load. This Voltage Regulator Module (VRM) efficiently steps down an input voltage to meet the specific output voltage requirements of the load. Additionally, bulk energy-storage output capacitors are included within the system to provide energy to the load during severe load transients when there is a large mismatch between the instantaneous load current and the instantaneous output current of the power stage of the VRM.

The core focus of this study is the Power Distribution Network (PDN), particularly the impact of the parasitic components contributed by the layout of the Printed Circuit Board (PCB) on power quality delivered to the load during high di/dt events. These parasitic elements, intrinsic to the physical design of the PCB, include parasitic resistances, inductances and capacitances which can have a non-negligible influence on the voltage delivered to the load. In this analysis the PDN block only describes the PCB parasitic elements that define the impedance between the output inductors and the load, and model the physical location of the connections to the discrete bulk capacitors. These discrete bulk capacitors are shown as external components and are explicitly not included in the PDN. This allows us to isolate the effects of the PCB layout parasitics on the performance of the power system from the impact of the number and quality of the bulk capacitors when handling the dynamic power demands of microprocessors with extremely high di/dt load transitions.

We note that while it is possible to include the discrete bulk energy-storage capacitors within the PDN for some analytical purposes, such an approach is not compatible with the procedure presented here for addressing the PDN challenge. In this procedure, it is important to exclude from the PDN all discrete capacitors that are mounted on the PCB or in the microprocessor package. As a result, the PDN represents only the parasitic impedances of the PCB, and the bulk capacitors are represented as discrete components on the top-level schematic.

Figure G.2 illustrates the importance of being able to simulate the performance of the VRM with its associated PDN when powering very high di/dt microprocessor loads. In the top grid we see the load current i_Load transient rising from ~ 80 A to ~ 613 A with a rise time of approximately 1.1 A/ns. Superimposed on that curve is the sum of all the output inductor currents i_Ltotal which equals the sum of the three phases i_{L_phN} being fed into the “North” side and the 4 phases i_{L_phS} being fed into the “South” side of the microprocessor package. We can see that the VRM is not able to ramp up its total output current iLtotal nearly fast enough to match the load. In fact, during this step load transient, the load current exceeds the total current iLtotal coming from all the output inductors by as much as 400 Amps. The load current, i_Load, exceeds i_Ltotal by more than 50 Amps for more than 2.2 μs. In order for the input voltage to the microprocessor not to dip too much during this transient this excess load current must be supplied by the bulk capacitors. To do this successfully the ESL and ESR of the bulk capacitors as well as the parasitic inductance and resistance of the connection introduced by the PCB layout must be managed very carefully.


	Figure G.2: Input voltage VCCIN to microprocessor under high di/dt load transient. Waveform VCCIN_Full shows effect of parasitic resistance, parasitic capacitance, and parasitic series inductance of Printed Circuit Board (PCB) layout (PDN) under a step load of ~530 A with slew rate of ~1.1 A/ns. VCCIN_Full shows the combined effects on the input voltage to the load of all parasitic elements of the PDN. VCCIN_R_only shows the effects of only the parasitic resistances of the PCB layout or PDN.

On the lower grid of Fig. G.2 is a plot of two curves. The curve labeled VCCIN_Full shows the input voltage to the microprocessor during this load transient with the full model of the PDN that includes all the parasitic resistances, inductances and capacitances of the PCB layout. The curve VCCIN_Ronly shows the resulting input voltage waveform if only the parasitic resistances of the PDN model are included in the simulation. The difference between these two curves shows the impact of the parasitic inductances of the PCB layout. The impact of the PCB parasitic capacitances is essentially negligible for our purposes. These two curves diverge when there is a significant di/dt rate of change in the load current. Otherwise, these two curves are very close to each other.

Remote sensing has long been used to compensate for resistive drops between the output of a power supply and the load. However, with the extremely high di/dt load transients of recent generations of high-performance microprocessors, the inductive impedance of the PDN can no longer be ignored.

During these severe load transients with di/dt’s of 1.1 A/ns, to meet the regulation requirements, the sum of all the effective series inductances between the output bulk capacitors and the input terminals to the load must be kept to a value on the order of 0.1 nH. This challenge to deliver on the order of 1000 A through a PDN with less than 0.1 nH of ESL is a bit breath taking and not for the faint of heart. It is not hard to understand why simulation tools are essential to master this design challenge within a time frame compatible with today’s very short development schedules.

When powering modern high performance microprocessors, the PCB layout and the placement, quality, and quantity of the bulk capacitors has become a critical dimension of the power supply system design. The design of the PDN has become too important and too sensitive, and the development schedules have become too short to be supported by trial-and-error design methods. Here we demonstrate a procedure to apply Power Supply System simulation to verify that a given Power Supply design with a given PDN will meet system requirements.

To accomplish this goal, we need a detailed simulation model of the VRM controller of Fig. G.1. To handle the demanding requirements of this application, these controllers typically employ highly nonlinear control strategies to handle the high di/dt load transients. They also will often shed phases of the Power Stage under very light load conditions to reduce power dissipation and improve operating efficiency at light loads. Consequently, these VRM simulation models can be very complex. In order to model these severe load transients these models must be time-domain switching models. Averaged models cannot accomplish this task.

We also need accurate simulation models of the PDN. Current methods to extract a Spice model of the PDN use PCB analysis tools that were originally created to address signal integrity applications for high-speed digital signals flowing through narrow PCB traces. These tools have now been adapted to analyze the PDN. Depending on the upper frequency of the requested analysis, the resulting simulation models can be quite complex as they attempt to model effects in the 10 GHz range. These high frequency PDN models can have more than 3000 to 4000 poles or similar number of equivalent inductors and capacitors. PDN models this complex will result in SIMPLIS system simulations that are impractically slow when considering the number of system simulations that must be completed in a reasonable time to meet ever shortening project schedules.

Fortunately, these extremely high frequency models are not needed to achieve accurate simulation results. Here we demonstrate how a simplified lower order model of the PDN can achieve very useful results with much faster simulation times that are compatible with demanding project schedules.

G.2 Overview of PDN Analysis Procedure

Here we present the outline of the PDN Analysis Procedure that we recommend addressing the PDN challenge described above.

Extract Spice netlist of PDN from PCB layout
G.4 Convert PDN Netlist to SIMPLIS and SIMetrix Compatible Netlists and Create Associated Symbol
Using SIMetrix PDN test bench, characterize performance of Full PDN and R-Only PDN using worst-case expected load-transient current waveform
Using SIMetrix testbench:
- Find optimum curve-fit values for Reduced-Order PDN model
- Compare performance of Full, R-Only, and the Reduced-Order PDN models with worst-case expected load-transient current waveform
Using SIMPLIS testbench with complete SIMPLIS converter model:
- Compare system performance of Full, R-Only, and Reduced-Order PDN models

In what follows we discuss each of these steps in the process.

G.3 Extract Spice netlist of PDN from PCB layout

A variety of tools are available to extract a Spice model of the parasitic resistances, inductances and capacitances associated with the portions of a PCB layout connecting the output inductors of the power stage with the input terminals of the microprocessor load. These tools can take as input the physical layout of the PCB and then calculate the associated PCB parasitic impedances.

The details of this PCB parasitic extraction process differ from one tool to the next and are not the subject of this document. However, there are several items that these tools have in common. Many of these tools have their origins in the field of Signal Integrity. Many of them perform their analysis of the PCB layout in the frequency domain and have as a possible output a set of s-parameters. S-parameters are only defined in the frequency domain and as such are not applicable for the time-domain analyses required for predicting VRM output-voltage performance under extremely high di/dt load transitions. Fortunately, many of these tools have supplementary applications that will convert the S-parameter data to an equivalent Spice model made up of passive R, L and C components and controlled sources. During the conversion process, it is essential that the resulting networks exhibit passive network behavior. It is also important to submit these mathematically derived models to a causality check so that they do not exhibit nonphysical behavior.

When creating the Spice Model of the PDN, it is tempting to think that it is desirable to specify that the valid upper frequency range of the PDN model be as high as possible. Some tools will provide models that are valid up to 10 GHz or higher. However, from a practical perspective, less is often more. PDN models that are valid to frequencies up to 1 to 10 GHz can result in Spice models with more than 4000 to 6000 equivalent parasitic inductors and capacitors. A PDN with this many energy storage elements will result in impractically long simulation times.

Based on our experience, we recommend applying these constraints to the PDN extraction process.

The resulting PDN Spice netlist should have:

No more than 10 -12 ports
No more than 100 poles (equivalent inductors and capacitors)
Purely passive network behavior
Passed a causality check

The tools for converting the s-parameter models to SPICE models are not the focus of this discussion, but a partial list of these tools include IdEM, Sigrity Broadband SPICE, Keysight Broadband SPICE Model Generator…

The PCB layout also defines the location of the bulk capacitors that are connected in parallel with the load. In order to minimize the number of ports of the PDN, it is important to group the capacitors into islands that reduce the number of ports of the PDN that connect to bulk capacitors to less than 6 or 7. For capacitors that occupy the same island of the PCB layout, it is important that all capacitors of the same type with the same values of C, ESR and ESL be grouped together in a single symbol using the Quantity feature as shown here.

The simulation speed is dramatically improved by using the Quantity feature rather than showing, in this example, 24 capacitors on the schematic in parallel. Bulk capacitors connected in parallel with the load via the PDN on different islands of the layout should be grouped with like capacitors on the same island.

Example of auto-generated PDN Spice model

In this exercise, we will briefly examine the contents of the output of one of these PCB layout extraction routines that result in a Spice subcircuit model of the PDN shown in the schematic of Fig, G.1.

1. Open the file PDN.cir in a text editor. You can observe the form and format of this Spice model of the PDN that we use in this study.

**********************************************************
** STATE-SPACE REALIZATION
** IN SPICE LANGUAGE
** This file is automatically generated
**********************************************************
** Created: 05-May-2021 by IdEM MP 12 (12.5.0)
**********************************************************
**
**********************************************************
** COMMENTS
**********************************************************
**
** Generated from: VR14_06A_MB_INT_10ohm_vsense_tie.spd
**
**  VCCIN_Vsense::VCCIN
**  VRTT::VCCIN
**  Vph_N::PVCCIN_CPU0
**  Vph_S::PVCCIN_CPU0
**  North_VR_Caps::PVCCIN_CPU0
**  South_VR_Caps::PVCCIN_CPU0
**  Top_Cavity_Caps::PVCCIN_CPU0
**  Btm_Cavity_Caps::PVCCIN_CPU0
**  Btm_VR_Caps_N::PVCCIN_CPU0
**  Btm_VR_Caps_S::PVCCIN_CPU0
** 
** Sigrity Suite Version: 19.0.4.01041.258722   004
** Computer Host Name: FM6SRDS2035
** 
** TouchstoneFormatFlag = 1
**  GNDNET GND
**  NETSLIST PVCCIN_CPU0, VCCIN
**  Port 2 = PKGJ1-AA12 VCCIN
**  Port 5 = BRDC1902-2 PVCCIN_CPU0
**  Port 6 = BRDC1679-2 PVCCIN_CPU0
**  Port 7 = BRDC1667-2 PVCCIN_CPU0
**  Port 8 = BRDC1771-2 PVCCIN_CPU0
**  Port 9 = BRDC1914-2 PVCCIN_CPU0
**  Port 10 = BRDC1757-2 PVCCIN_CPU0
** 
**
**********************************************************
**
**
**---------------------------
** Options Used in IdEM Flow
**---------------------------
**
** Fitting Options **
**
** Bandwidth: 5.0000e+08 Hz
** Order: [3 2 9] 
** SplitType: none 
** tol: 1.0000e-03 
**
**---------------------------
**
** Passivity Options **
**
** Alg: SOC+HAM 
**    Max SOC it: 50 
**    Max HAM it: 50 
** Freq sampling: manual
**    In-band samples: 200
**    Off-band samples: 100
** Optimization method: Model based
**
**---------------------------
**
** Netlist Options **
**
** Netlist format: SPICE standard
** Port reference: common
** Resistor synthesis: standard
**
**---------------------------
**

**************************************************************************
***{
***
*** The following was added by SIMPLIS Technologies, Inc. as a brief
***	description of a typical SPICE subcircuit file modeling a PDN
***	(Power Distribution Network) and how such a file can be converted
***	to be used by SIMPLIS in the SIMetrix/SIMPLIS environment.
***
***
*** This is an example SPICE subcircuit model for a 10-port PDN.
***
*** A SPICE subcircuit model for a PDN is typically generated by tools that
***	model the frequency-domain scattering characteristics of the
***	physical layout of the conductor/via of the printed circuit board,
***	with the possible inclusion of explicit capacitors and resistors
***	that are not parasitics.
***
*** Since SPICE usually works with node names and SIMPLIS works with node
***	numbers, SIMPLIS Technologies, Inc. has developed a PDN Parser
***	Tool to convert the SPICE subcircuit model into a subcircuit model
***	usable by SIMPLIS.
***
*** Another function of the PDN Parser Tool is to generate a SIMetrix /
***	SIMPLIS symbol for the PDN so that the symbol can be placed on a
***	schematic in SIMetrix/SIMPLIS to represent the PDN.
***
**************************************************************************

**************************************************************************
***
*** The following was added by SIMPLIS Technologies, Inc.
***
***
*** This is a file in SPICE format.  If the first non white-space
***	character in a line is the asterisk (*), then this line is a
***	comment line.  If the first character in a line is the plus
***	sign (+), then this line is a line of continuation.
***
*** Hence, the following three lines (without the three leading asterisks
***	and the tab character)
***
***	.subckt PDN_subckt a_1 a_2 a_3
***	+  a_4 a_5 a_6
***	+  a_7 a_8 a_9 a_10 ref
***
*** are equivalent to the following line (without the three leading
***	asterisks and the tab character)
***
***	.subckt PDN_subckt a_1 a_2 a_3 a_4 a_5 a_6 a_7 a_8 a_9 a_10 ref
***
**************************************************************************

**************************************************************************
***
*** NOTE from the particular tool generating this SPICE subcircuit file:
***
***	a_i  --> input node associated to the port i
***	ref  --> reference node, common for all the input nodes
***
***
*** The effective/example subcircuit line is:
***
***	.subckt PDN_subckt a_1 a_2 a_3 a_4 a_5 a_6 a_7 a_8 a_9 a_10 ref
***
***
*** The following was added by SIMPLIS Technologies, Inc.
***
***
*** Without any additional information, the PDN Parser Tool will create a
***	symbol with pin names of a_1, a_2, ..., ref.
***
*** If you edit the SPICE model file for the PDN and add additional
***	information, you can override the default pin names with more
***	meaningful pin names in the symbol.
***
*** The specification of desired pin names in your symbol are defined
***	through comment lines BEFORE the first .subckt line in this file.
***	Such a comment line must have at least four fields in the line,
***	where each field is a group of non white-space characters and the
***	fields are separated by one or more white-space characters.  The
***	space character and the TAB character are considered white-space
***	characters.
***
***	    FIELD #1
***		One ore more asterisk character(s) and this field MUST
***		start at the first column position in the line.
***
***	    FIELD #2
***		The keyword SIMPLIS_PDN_PIN_NAME
***
***	    FIELD #3
***		The node position in the .subckt line, with the first
***		node position denoted as position 1.
***
***	    FIELD #4
***		The preferred pin name in the symbol for this node.  It is
***		recommended that the pin names contain only alphanumeric
***		characters and the underscore (_) character.  The first
***		character in a pin name should be an alphabet.
***
***
*** The following two example lines below, if the three leading asterisks
***	and the following tab characters were removed, will lead to a
***	symbol with a pin name of ABC for node a_1, and a pin name of DEF
***	for node a_3 for our example .subckt statement.  As there were no
***	SIMPLIS_PDN_PIN_NAME statements defined for the other nodes on the
***	example .subckt line, the node names for these nodes will be used
***	as the pin names in the symbol.
***
***	Actual start of line
***	|
***	v
***	*	SIMPLIS_PDN_PIN_NAME:		1	ABC
***	******	SIMPLIS_PDN_PIN_NAME:		3	DEF
***
***
*** When this subcircuit file is fed into the SIMPLIS PDN Parser Tool as
***	the input file, the symbol created will have pin names of VOSENP,
***	VCCIN, Ph_N, Ph_S, Caps_1, Caps_2, Caps_3, Caps_4, Caps_5, Caps_6,
***	and ref because of the following 10 lines that contain the
***	SIMPLIS_PDN_PIN_NAME keyword:
***
***
***	SIMPLIS_PDN_PIN_NAME:		1	VOSENP
***	SIMPLIS_PDN_PIN_NAME:		2	VCCIN
***	SIMPLIS_PDN_PIN_NAME:		3	Ph_N
***	SIMPLIS_PDN_PIN_NAME:		4	Ph_S
***	SIMPLIS_PDN_PIN_NAME:		5	Caps_1
***	SIMPLIS_PDN_PIN_NAME:		6	Caps_2
***	SIMPLIS_PDN_PIN_NAME:		7	Caps_3
***	SIMPLIS_PDN_PIN_NAME:		8	Caps_4
***	SIMPLIS_PDN_PIN_NAME:		9	Caps_5
***	SIMPLIS_PDN_PIN_NAME:		10	Caps_6
***
***}
**************************************************************************


**********************************************************
* NOTE:
* a_i  --> input node associated to the port i 
* ref  --> reference node, common for all the input nodes 
**********************************************************

***********************************
* Interface (ports specification) *
***********************************
.subckt PDN_subckt
+  a_1 a_2 a_3 a_4 a_5 a_6 a_7 a_8 a_9 a_10 ref
***********************************


******************************************
* Main circuit connected to output nodes *
******************************************

* Port 1
VI_1 a_1 NI_1 0
RI_1 NI_1 ref 1.0000000000000000e+01
GC_1_1 ref NI_1 NS_1 0 -8.6267797685159894e-02
GC_1_2 ref NI_1 NS_2 0 -3.1695042667834995e-02
GC_1_3 ref NI_1 NS_3 0 8.9109795569324595e-06
GC_1_4 ref NI_1 NS_4 0 4.6362351844730615e-06
GC_1_5 ref NI_1 NS_5 0 -2.4338482544688482e-06
GC_1_6 ref NI_1 NS_6 0 4.8802468290969379e-07
GC_1_7 ref NI_1 NS_7 0 -1.1600208064491790e-06
GC_1_8 ref NI_1 NS_8 0 3.7847750692510811e-05
GC_1_9 ref NI_1 NS_9 0 -5.5735222338960090e-06
GC_1_10 ref NI_1 NS_10 0 -3.3098650194660351e-03
GC_1_11 ref NI_1 NS_11 0 4.9390447202489886e-04
GC_1_12 ref NI_1 NS_12 0 9.0147033246282097e-06
GC_1_13 ref NI_1 NS_13 0 8.1961743230962946e-06
GC_1_14 ref NI_1 NS_14 0 6.1765800840654062e-07
GC_1_15 ref NI_1 NS_15 0 7.2021614862563572e-07
GC_1_16 ref NI_1 NS_16 0 1.4229650136663458e-06
GC_1_17 ref NI_1 NS_17 0 3.7663889477511700e-05
GC_1_18 ref NI_1 NS_18 0 -1.1671942468833216e-06
GC_1_19 ref NI_1 NS_19 0 1.0494059227934194e-03
GC_1_20 ref NI_1 NS_20 0 1.0891550747099870e-04
GC_1_21 ref NI_1 NS_21 0 9.0172237810523149e-06
GC_1_22 ref NI_1 NS_22 0 -1.7756979378388187e-05
GC_1_23 ref NI_1 NS_23 0 2.9206105331601790e-06
GC_1_24 ref NI_1 NS_24 0 5.5178779040142569e-06
GC_1_25 ref NI_1 NS_25 0 1.4270540148621404e-07
GC_1_26 ref NI_1 NS_26 0 -1.4255587073852486e-06
GC_1_27 ref NI_1 NS_27 0 -1.7544975475673101e-08
GC_1_28 ref NI_1 NS_28 0 -1.3092249497200517e-02
GC_1_29 ref NI_1 NS_29 0 9.8520195076295882e-05
GC_1_30 ref NI_1 NS_30 0 9.0235673551378205e-06
GC_1_31 ref NI_1 NS_31 0 -9.8103360261359555e-06
GC_1_32 ref NI_1 NS_32 0 6.5740552102892825e-07
GC_1_33 ref NI_1 NS_33 0 -4.5673600819087673e-06
GC_1_34 ref NI_1 NS_34 0 -9.4657918506147485e-07
GC_1_35 ref NI_1 NS_35 0 7.7611323642627685e-06
GC_1_36 ref NI_1 NS_36 0 -8.9401257372897944e-07
GC_1_37 ref NI_1 NS_37 0 -1.9069202617826666e-03
GC_1_38 ref NI_1 NS_38 0 1.6582180944860601e-04
GC_1_39 ref NI_1 NS_39 0 9.0185703165906122e-06
GC_1_40 ref NI_1 NS_40 0 -1.8687812308921454e-05
GC_1_41 ref NI_1 NS_41 0 3.0744166141653231e-06
GC_1_42 ref NI_1 NS_42 0 5.5859351292285337e-06
GC_1_43 ref NI_1 NS_43 0 1.0999720688254255e-07
GC_1_44 ref NI_1 NS_44 0 5.3726852537005971e-06
GC_1_45 ref NI_1 NS_45 0 -3.2595331401758057e-07
GC_1_46 ref NI_1 NS_46 0 -1.2719714676119959e-02
GC_1_47 ref NI_1 NS_47 0 2.6914876912967898e-04
GC_1_48 ref NI_1 NS_48 0 9.0234390627329261e-06
GC_1_49 ref NI_1 NS_49 0 -7.0392242707099411e-06
GC_1_50 ref NI_1 NS_50 0 5.7018943734817043e-07
GC_1_51 ref NI_1 NS_51 0 -3.1674662614245012e-06
GC_1_52 ref NI_1 NS_52 0 -4.6496708419361174e-07
GC_1_53 ref NI_1 NS_53 0 1.7720071822318034e-05
GC_1_54 ref NI_1 NS_54 0 -1.1692744504199971e-06
GC_1_55 ref NI_1 NS_55 0 -6.1352610993221229e-04
GC_1_56 ref NI_1 NS_56 0 6.0707521227886231e-05
GC_1_57 ref NI_1 NS_57 0 9.0166123785306882e-06
GC_1_58 ref NI_1 NS_58 0 -1.1836456996217053e-07
GC_1_59 ref NI_1 NS_59 0 -3.5640678171593891e-08
GC_1_60 ref NI_1 NS_60 0 1.7632543924295680e-06
GC_1_61 ref NI_1 NS_61 0 2.1265937318331874e-07
GC_1_62 ref NI_1 NS_62 0 3.0628959093053036e-05
GC_1_63 ref NI_1 NS_63 0 -1.8480754892416378e-06
GC_1_64 ref NI_1 NS_64 0 -8.3328785078004748e-04
GC_1_65 ref NI_1 NS_65 0 9.7920179120612180e-05
GC_1_66 ref NI_1 NS_66 0 9.0166067328772064e-06
GC_1_67 ref NI_1 NS_67 0 -1.1972240605360346e-06
GC_1_68 ref NI_1 NS_68 0 1.1856682444338475e-07
GC_1_69 ref NI_1 NS_69 0 1.8810350983420390e-06
GC_1_70 ref NI_1 NS_70 0 2.1358983504161338e-07
GC_1_71 ref NI_1 NS_71 0 2.9598335832023110e-05
GC_1_72 ref NI_1 NS_72 0 -1.8202467305244511e-06
GC_1_73 ref NI_1 NS_73 0 -5.0302668975740908e-03
GC_1_74 ref NI_1 NS_74 0 2.2390301019291966e-04
GC_1_75 ref NI_1 NS_75 0 9.0198063392198828e-06
GC_1_76 ref NI_1 NS_76 0 -1.8742380972260078e-05
GC_1_77 ref NI_1 NS_77 0 2.9625665916699423e-06
GC_1_78 ref NI_1 NS_78 0 5.6139050859731395e-06
GC_1_79 ref NI_1 NS_79 0 7.3392732479095726e-08
GC_1_80 ref NI_1 NS_80 0 7.1672759455379924e-06
GC_1_81 ref NI_1 NS_81 0 -3.2161832621759689e-07
GC_1_82 ref NI_1 NS_82 0 -1.6061220581368239e-02
GC_1_83 ref NI_1 NS_83 0 2.5103826054070623e-04
GC_1_84 ref NI_1 NS_84 0 9.0258318610652617e-06
GC_1_85 ref NI_1 NS_85 0 -9.2864546088353147e-06
GC_1_86 ref NI_1 NS_86 0 4.6625219837504974e-07
GC_1_87 ref NI_1 NS_87 0 -3.3236262873932422e-06
GC_1_88 ref NI_1 NS_88 0 -6.2224219727727657e-07
GC_1_89 ref NI_1 NS_89 0 1.7356044019333759e-05
GC_1_90 ref NI_1 NS_90 0 -1.0579662627130972e-06
GD_1_1 ref NI_1 NA_1 0 6.2057089247737218e-01
GD_1_2 ref NI_1 NA_2 0 9.4073000096558241e-04
GD_1_3 ref NI_1 NA_3 0 -7.1507407511151484e-03
GD_1_4 ref NI_1 NA_4 0 5.5437299927774235e-02
GD_1_5 ref NI_1 NA_5 0 4.3237928004451979e-03
GD_1_6 ref NI_1 NA_6 0 4.8963781282800246e-02
GD_1_7 ref NI_1 NA_7 0 4.0652484331756223e-04
GD_1_8 ref NI_1 NA_8 0 4.0771928372521570e-04
GD_1_9 ref NI_1 NA_9 0 1.6615060594218776e-02
GD_1_10 ref NI_1 NA_10 0 6.4343757103560467e-02
*
* Port 2
VI_2 a_2 NI_2 0
RI_2 NI_2 ref 1.0000000000000000e+01
GC_2_1 ref NI_2 NS_1 0 -3.3098650194660680e-03
GC_2_2 ref NI_2 NS_2 0 4.9390447202490037e-04
GC_2_3 ref NI_2 NS_3 0 9.0147033246282114e-06
GC_2_4 ref NI_2 NS_4 0 8.1961743230962912e-06
GC_2_5 ref NI_2 NS_5 0 6.1765800840654020e-07
GC_2_6 ref NI_2 NS_6 0 7.2021614862563815e-07
GC_2_7 ref NI_2 NS_7 0 1.4229650136663443e-06
GC_2_8 ref NI_2 NS_8 0 3.7663889477511707e-05
GC_2_9 ref NI_2 NS_9 0 -1.1671942468833219e-06
GC_2_10 ref NI_2 NS_10 0 -9.1443571030223273e-03
GC_2_11 ref NI_2 NS_11 0 -4.0278181062021608e-04
GC_2_12 ref NI_2 NS_12 0 8.9857922465002056e-06
GC_2_13 ref NI_2 NS_13 0 8.6304262224935433e-06
GC_2_14 ref NI_2 NS_14 0 -4.0230609463657800e-07
GC_2_15 ref NI_2 NS_15 0 1.0146036759866554e-06
GC_2_16 ref NI_2 NS_16 0 -5.2985632962467365e-07
GC_2_17 ref NI_2 NS_17 0 3.8773974173881492e-05
GC_2_18 ref NI_2 NS_18 0 6.4247028747276582e-07
GC_2_19 ref NI_2 NS_19 0 -2.2065345067888912e-03
GC_2_20 ref NI_2 NS_20 0 -3.3557985960857592e-05
GC_2_21 ref NI_2 NS_21 0 9.0053729726399258e-06
GC_2_22 ref NI_2 NS_22 0 -1.8866392587987217e-05
GC_2_23 ref NI_2 NS_23 0 -8.5530294128342576e-07
GC_2_24 ref NI_2 NS_24 0 4.7319385239545600e-06
GC_2_25 ref NI_2 NS_25 0 3.6328674223072876e-07
GC_2_26 ref NI_2 NS_26 0 -1.2757545909645361e-06
GC_2_27 ref NI_2 NS_27 0 -4.1201547283237075e-07
GC_2_28 ref NI_2 NS_28 0 -1.6714798321519220e-02
GC_2_29 ref NI_2 NS_29 0 5.5753519317568721e-04
GC_2_30 ref NI_2 NS_30 0 9.0099210581159832e-06
GC_2_31 ref NI_2 NS_31 0 -1.0149466892259926e-05
GC_2_32 ref NI_2 NS_32 0 2.4297512171894839e-07
GC_2_33 ref NI_2 NS_33 0 -3.8706989579682522e-06
GC_2_34 ref NI_2 NS_34 0 -6.9071644142834058e-07
GC_2_35 ref NI_2 NS_35 0 7.6231888102927786e-06
GC_2_36 ref NI_2 NS_36 0 2.7188130785769556e-07
GC_2_37 ref NI_2 NS_37 0 -6.4223667118143146e-03
GC_2_38 ref NI_2 NS_38 0 1.1325885345753127e-04
GC_2_39 ref NI_2 NS_39 0 9.0061752846605501e-06
GC_2_40 ref NI_2 NS_40 0 -1.9874314394311989e-05
GC_2_41 ref NI_2 NS_41 0 -8.3811020978124109e-07
GC_2_42 ref NI_2 NS_42 0 4.7756778874707002e-06
GC_2_43 ref NI_2 NS_43 0 4.1089909537160262e-07
GC_2_44 ref NI_2 NS_44 0 5.5772304615432734e-06
GC_2_45 ref NI_2 NS_45 0 -1.1790975572598164e-07
GC_2_46 ref NI_2 NS_46 0 -1.3911213122728350e-02
GC_2_47 ref NI_2 NS_47 0 4.4197981775417574e-04
GC_2_48 ref NI_2 NS_48 0 9.0076104352446703e-06
GC_2_49 ref NI_2 NS_49 0 -7.3061839586875850e-06
GC_2_50 ref NI_2 NS_50 0 2.0876538998660666e-08
GC_2_51 ref NI_2 NS_51 0 -2.6678998222815130e-06
GC_2_52 ref NI_2 NS_52 0 -5.0202021112942395e-07
GC_2_53 ref NI_2 NS_53 0 1.7833281423929039e-05
GC_2_54 ref NI_2 NS_54 0 5.1825127612618784e-07
GC_2_55 ref NI_2 NS_55 0 -1.2201618426883704e-04
GC_2_56 ref NI_2 NS_56 0 -3.0145027242120960e-05
GC_2_57 ref NI_2 NS_57 0 9.0039833991268992e-06
GC_2_58 ref NI_2 NS_58 0 -1.6477350666071558e-07
GC_2_59 ref NI_2 NS_59 0 -6.6341233419396380e-07
GC_2_60 ref NI_2 NS_60 0 1.5022797165107343e-06
GC_2_61 ref NI_2 NS_61 0 1.8308691009460368e-08
GC_2_62 ref NI_2 NS_62 0 3.1146435976016691e-05
GC_2_63 ref NI_2 NS_63 0 4.4038250269697667e-07
GC_2_64 ref NI_2 NS_64 0 2.6217819915351091e-04
GC_2_65 ref NI_2 NS_65 0 6.1305915814840481e-06
GC_2_66 ref NI_2 NS_66 0 9.0045112555313580e-06
GC_2_67 ref NI_2 NS_67 0 -1.3000935170316406e-06
GC_2_68 ref NI_2 NS_68 0 -6.7420022972779699e-07
GC_2_69 ref NI_2 NS_69 0 1.5969279291525925e-06
GC_2_70 ref NI_2 NS_70 0 6.3140605369852125e-08
GC_2_71 ref NI_2 NS_71 0 3.0100767414671035e-05
GC_2_72 ref NI_2 NS_72 0 4.0059224890391213e-07
GC_2_73 ref NI_2 NS_73 0 -1.0808550191781847e-02
GC_2_74 ref NI_2 NS_74 0 2.2115128389801520e-04
GC_2_75 ref NI_2 NS_75 0 9.0049581092356858e-06
GC_2_76 ref NI_2 NS_76 0 -1.9890592830976056e-05
GC_2_77 ref NI_2 NS_77 0 -9.0872149630585791e-07
GC_2_78 ref NI_2 NS_78 0 4.7967578446840201e-06
GC_2_79 ref NI_2 NS_79 0 4.0432944218194290e-07
GC_2_80 ref NI_2 NS_80 0 7.3729627976287797e-06
GC_2_81 ref NI_2 NS_81 0 4.8324483084342229e-08
GC_2_82 ref NI_2 NS_82 0 -1.7520331460230732e-02
GC_2_83 ref NI_2 NS_83 0 4.6644592360619024e-04
GC_2_84 ref NI_2 NS_84 0 9.0054193807990271e-06
GC_2_85 ref NI_2 NS_85 0 -9.6162138566756280e-06
GC_2_86 ref NI_2 NS_86 0 -2.2666460113412741e-07
GC_2_87 ref NI_2 NS_87 0 -2.8281573294987830e-06
GC_2_88 ref NI_2 NS_88 0 -5.9007938645064709e-07
GC_2_89 ref NI_2 NS_89 0 1.7406179993585282e-05
GC_2_90 ref NI_2 NS_90 0 6.4175417379562041e-07
GD_2_1 ref NI_2 NA_1 0 9.4073000096567662e-04
GD_2_2 ref NI_2 NA_2 0 -5.8045203243176746e-01
GD_2_3 ref NI_2 NA_3 0 1.1012934791396646e-02
GD_2_4 ref NI_2 NA_4 0 5.9554804765230840e-02
GD_2_5 ref NI_2 NA_5 0 2.5796007360134942e-02
GD_2_6 ref NI_2 NA_6 0 5.0164962827198074e-02
GD_2_7 ref NI_2 NA_7 0 1.3849606921245586e-03
GD_2_8 ref NI_2 NA_8 0 -1.3192226213823248e-03
GD_2_9 ref NI_2 NA_9 0 4.2441749921709390e-02
GD_2_10 ref NI_2 NA_10 0 6.5635371833338285e-02
*
* Port 3
VI_3 a_3 NI_3 0
RI_3 NI_3 ref 1.0000000000000000e+01
GC_3_1 ref NI_3 NS_1 0 1.0494059227934129e-03
GC_3_2 ref NI_3 NS_2 0 1.0891550747099919e-04
GC_3_3 ref NI_3 NS_3 0 9.0172237810523149e-06
GC_3_4 ref NI_3 NS_4 0 -1.7756979378388187e-05
GC_3_5 ref NI_3 NS_5 0 2.9206105331601765e-06
GC_3_6 ref NI_3 NS_6 0 5.5178779040142543e-06
GC_3_7 ref NI_3 NS_7 0 1.4270540148621656e-07
GC_3_8 ref NI_3 NS_8 0 -1.4255587073852492e-06
GC_3_9 ref NI_3 NS_9 0 -1.7544975475672115e-08
GC_3_10 ref NI_3 NS_10 0 -2.2065345067889125e-03
GC_3_11 ref NI_3 NS_11 0 -3.3557985960857640e-05
GC_3_12 ref NI_3 NS_12 0 9.0053729726399258e-06
GC_3_13 ref NI_3 NS_13 0 -1.8866392587987200e-05
GC_3_14 ref NI_3 NS_14 0 -8.5530294128339040e-07
GC_3_15 ref NI_3 NS_15 0 4.7319385239545787e-06
GC_3_16 ref NI_3 NS_16 0 3.6328674223070886e-07
GC_3_17 ref NI_3 NS_17 0 -1.2757545909645259e-06
GC_3_18 ref NI_3 NS_18 0 -4.1201547283237916e-07
GC_3_19 ref NI_3 NS_19 0 -4.3543451992635207e-02
GC_3_20 ref NI_3 NS_20 0 -9.8828939859576365e-04
GC_3_21 ref NI_3 NS_21 0 8.9801747975822419e-06
GC_3_22 ref NI_3 NS_22 0 4.0704278975024792e-05
GC_3_23 ref NI_3 NS_23 0 1.6735639300139574e-06
GC_3_24 ref NI_3 NS_24 0 3.3673070396307742e-05
GC_3_25 ref NI_3 NS_25 0 1.8975627765101199e-07
GC_3_26 ref NI_3 NS_26 0 1.0330775463587333e-06
GC_3_27 ref NI_3 NS_27 0 -1.3673661981387673e-06
GC_3_28 ref NI_3 NS_28 0 -3.4776937212077901e-03
GC_3_29 ref NI_3 NS_29 0 1.2555738602249971e-04
GC_3_30 ref NI_3 NS_30 0 9.0157232927143767e-06
GC_3_31 ref NI_3 NS_31 0 2.3914140415663666e-05
GC_3_32 ref NI_3 NS_32 0 5.6265077650015187e-07
GC_3_33 ref NI_3 NS_33 0 -2.7982586369629624e-05
GC_3_34 ref NI_3 NS_34 0 -1.3171126419348591e-06
GC_3_35 ref NI_3 NS_35 0 5.2730374738329440e-08
GC_3_36 ref NI_3 NS_36 0 -6.9818028635982415e-07
GC_3_37 ref NI_3 NS_37 0 1.7034562663475521e-02
GC_3_38 ref NI_3 NS_38 0 -7.2345512627045787e-04
GC_3_39 ref NI_3 NS_39 0 8.9913003157722765e-06
GC_3_40 ref NI_3 NS_40 0 4.3076111940243213e-05
GC_3_41 ref NI_3 NS_41 0 1.9048905046994239e-06
GC_3_42 ref NI_3 NS_42 0 3.3856528458217794e-05
GC_3_43 ref NI_3 NS_43 0 2.4672057783982279e-07
GC_3_44 ref NI_3 NS_44 0 3.9894070527905772e-07
GC_3_45 ref NI_3 NS_45 0 -9.2522580519917488e-07
GC_3_46 ref NI_3 NS_46 0 -9.5415251455271844e-03
GC_3_47 ref NI_3 NS_47 0 3.8462591780560049e-04
GC_3_48 ref NI_3 NS_48 0 9.0165550653637313e-06
GC_3_49 ref NI_3 NS_49 0 1.7509334241665840e-05
GC_3_50 ref NI_3 NS_50 0 2.8915134240290087e-07
GC_3_51 ref NI_3 NS_51 0 -1.9437971587731361e-05
GC_3_52 ref NI_3 NS_52 0 -6.9409952770187027e-07
GC_3_53 ref NI_3 NS_53 0 -6.2573848111358059e-07
GC_3_54 ref NI_3 NS_54 0 -2.2653085063232666e-07
GC_3_55 ref NI_3 NS_55 0 6.6116542387365416e-03
GC_3_56 ref NI_3 NS_56 0 -5.6901123578366395e-05
GC_3_57 ref NI_3 NS_57 0 9.0060347570439581e-06
GC_3_58 ref NI_3 NS_58 0 -1.4418683705395469e-07
GC_3_59 ref NI_3 NS_59 0 3.1751908707567522e-07
GC_3_60 ref NI_3 NS_60 0 1.0067910808034622e-05
GC_3_61 ref NI_3 NS_61 0 2.9922307546074186e-07
GC_3_62 ref NI_3 NS_62 0 -9.7684118619394558e-07
GC_3_63 ref NI_3 NS_63 0 -3.8519549839380506e-07
GC_3_64 ref NI_3 NS_64 0 7.2615118140603452e-03
GC_3_65 ref NI_3 NS_65 0 -5.0210543662863665e-05
GC_3_66 ref NI_3 NS_66 0 9.0056956164157562e-06
GC_3_67 ref NI_3 NS_67 0 2.4211745584587793e-06
GC_3_68 ref NI_3 NS_68 0 4.7844295429191583e-07
GC_3_69 ref NI_3 NS_69 0 1.0803387283146924e-05
GC_3_70 ref NI_3 NS_70 0 3.0559821951673026e-07
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GC_3_89 ref NI_3 NS_89 0 -9.7276054362740445e-07
GC_3_90 ref NI_3 NS_90 0 2.6608758379812192e-07
GD_3_1 ref NI_3 NA_1 0 -7.1507407511151129e-03
GD_3_2 ref NI_3 NA_2 0 1.1012934791396721e-02
GD_3_3 ref NI_3 NA_3 0 -4.1076899123876709e-01
GD_3_4 ref NI_3 NA_4 0 1.2042281284224720e-02
GD_3_5 ref NI_3 NA_5 0 -5.5989674964219742e-02
GD_3_6 ref NI_3 NA_6 0 3.2147866251665783e-02
GD_3_7 ref NI_3 NA_7 0 -2.7688431280543060e-02
GD_3_8 ref NI_3 NA_8 0 -3.0762727937316187e-02
GD_3_9 ref NI_3 NA_9 0 -8.8950824702832693e-02
GD_3_10 ref NI_3 NA_10 0 4.8811779734872607e-02
*
* Port 4
VI_4 a_4 NI_4 0
RI_4 NI_4 ref 1.0000000000000000e+01
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GD_4_1 ref NI_4 NA_1 0 5.5437299927774353e-02
GD_4_2 ref NI_4 NA_2 0 5.9554804765230999e-02
GD_4_3 ref NI_4 NA_3 0 1.2042281284224644e-02
GD_4_4 ref NI_4 NA_4 0 -4.6634707500615025e-01
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GD_4_6 ref NI_4 NA_6 0 -8.4682848726227947e-03
GD_4_7 ref NI_4 NA_7 0 3.8337132136777821e-02
GD_4_8 ref NI_4 NA_8 0 3.4362172378454334e-02
GD_4_9 ref NI_4 NA_9 0 -8.7325356282884591e-03
GD_4_10 ref NI_4 NA_10 0 1.3353194813904362e-03
*
* Port 5
VI_5 a_5 NI_5 0
RI_5 NI_5 ref 1.0000000000000000e+01
GC_5_1 ref NI_5 NS_1 0 -1.9069202617826755e-03
GC_5_2 ref NI_5 NS_2 0 1.6582180944860607e-04
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GC_5_7 ref NI_5 NS_7 0 1.0999720688254228e-07
GC_5_8 ref NI_5 NS_8 0 5.3726852537005962e-06
GC_5_9 ref NI_5 NS_9 0 -3.2595331401758073e-07
GC_5_10 ref NI_5 NS_10 0 -6.4223667118143831e-03
GC_5_11 ref NI_5 NS_11 0 1.1325885345753319e-04
GC_5_12 ref NI_5 NS_12 0 9.0061752846605501e-06
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GC_5_23 ref NI_5 NS_23 0 1.9048905046994265e-06
GC_5_24 ref NI_5 NS_24 0 3.3856528458217801e-05
GC_5_25 ref NI_5 NS_25 0 2.4672057783981867e-07
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GC_5_31 ref NI_5 NS_31 0 2.5168732609527663e-05
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GC_5_70 ref NI_5 NS_70 0 3.1600549760124676e-07
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GC_5_90 ref NI_5 NS_90 0 3.2668031266109363e-07
GD_5_1 ref NI_5 NA_1 0 4.3237928004452430e-03
GD_5_2 ref NI_5 NA_2 0 2.5796007360135188e-02
GD_5_3 ref NI_5 NA_3 0 -5.5989674964220193e-02
GD_5_4 ref NI_5 NA_4 0 -6.9028055489588156e-04
GD_5_5 ref NI_5 NA_5 0 -4.2103474608866082e-01
GD_5_6 ref NI_5 NA_6 0 4.3423671041051944e-02
GD_5_7 ref NI_5 NA_7 0 -8.8280354409099732e-03
GD_5_8 ref NI_5 NA_8 0 -1.1249709020995006e-02
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GD_5_10 ref NI_5 NA_10 0 8.0261604927659588e-02
*
* Port 6
VI_6 a_6 NI_6 0
RI_6 NI_6 ref 1.0000000000000000e+01
GC_6_1 ref NI_6 NS_1 0 -1.2719714676119967e-02
GC_6_2 ref NI_6 NS_2 0 2.6914876912967898e-04
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GC_6_4 ref NI_6 NS_4 0 -7.0392242707099394e-06
GC_6_5 ref NI_6 NS_5 0 5.7018943734816947e-07
GC_6_6 ref NI_6 NS_6 0 -3.1674662614244966e-06
GC_6_7 ref NI_6 NS_7 0 -4.6496708419361571e-07
GC_6_8 ref NI_6 NS_8 0 1.7720071822318034e-05
GC_6_9 ref NI_6 NS_9 0 -1.1692744504199986e-06
GC_6_10 ref NI_6 NS_10 0 -1.3911213122728491e-02
GC_6_11 ref NI_6 NS_11 0 4.4197981775418019e-04
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GC_6_28 ref NI_6 NS_28 0 6.8860540724009125e-03
GC_6_29 ref NI_6 NS_29 0 -8.0053587785672211e-04
GC_6_30 ref NI_6 NS_30 0 9.0061775211329981e-06
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GC_6_32 ref NI_6 NS_32 0 -1.0191164244283252e-07
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GC_6_35 ref NI_6 NS_35 0 3.4581923998000102e-06
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*
* Port 7
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GD_7_4 ref NI_7 NA_4 0 3.8337132136778369e-02
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GD_7_6 ref NI_7 NA_6 0 5.2778514611757373e-02
GD_7_7 ref NI_7 NA_7 0 -3.7579684494547133e-01
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GD_7_9 ref NI_7 NA_9 0 5.9271946388552198e-03
GD_7_10 ref NI_7 NA_10 0 7.9689551015241944e-02
*
* Port 8
VI_8 a_8 NI_8 0
RI_8 NI_8 ref 1.0000000000000000e+01
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*
* Port 9
VI_9 a_9 NI_9 0
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*
* Port 10
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GC_10_79 ref NI_10 NS_79 0 -6.6230560085091827e-07
GC_10_80 ref NI_10 NS_80 0 3.2179114992299652e-06
GC_10_81 ref NI_10 NS_81 0 3.0286402899999302e-07
GC_10_82 ref NI_10 NS_82 0 -6.4594533478451233e-02
GC_10_83 ref NI_10 NS_83 0 -1.0660909913113403e-03
GC_10_84 ref NI_10 NS_84 0 8.9911653049222036e-06
GC_10_85 ref NI_10 NS_85 0 1.0437603406379908e-05
GC_10_86 ref NI_10 NS_86 0 7.5575595208938042e-07
GC_10_87 ref NI_10 NS_87 0 1.2105137516333903e-05
GC_10_88 ref NI_10 NS_88 0 4.5812299240997361e-07
GC_10_89 ref NI_10 NS_89 0 7.9799693143995328e-06
GC_10_90 ref NI_10 NS_90 0 3.8597065700773107e-09
GD_10_1 ref NI_10 NA_1 0 6.4343757103560509e-02
GD_10_2 ref NI_10 NA_2 0 6.5635371833338965e-02
GD_10_3 ref NI_10 NA_3 0 4.8811779734871774e-02
GD_10_4 ref NI_10 NA_4 0 1.3353194813910691e-03
GD_10_5 ref NI_10 NA_5 0 8.0261604927659519e-02
GD_10_6 ref NI_10 NA_6 0 4.5621929783173296e-02
GD_10_7 ref NI_10 NA_7 0 7.9689551015241805e-02
GD_10_8 ref NI_10 NA_8 0 7.9513368928699688e-02
GD_10_9 ref NI_10 NA_9 0 8.9728901464718111e-02
GD_10_10 ref NI_10 NA_10 0 -3.1442276035665367e-01
*
******************************************


********************************
* Synthesis of impinging waves *
********************************

* Impinging wave, port 1
RA_1 NA_1 0 1.5811388300841898e+00
FA_1 0 NA_1 VI_1 1.0
GA_1 0 NA_1 a_1 ref 1.0000000000000001e-01
*
* Impinging wave, port 2
RA_2 NA_2 0 1.5811388300841898e+00
FA_2 0 NA_2 VI_2 1.0
GA_2 0 NA_2 a_2 ref 1.0000000000000001e-01
*
* Impinging wave, port 3
RA_3 NA_3 0 1.5811388300841898e+00
FA_3 0 NA_3 VI_3 1.0
GA_3 0 NA_3 a_3 ref 1.0000000000000001e-01
*
* Impinging wave, port 4
RA_4 NA_4 0 1.5811388300841898e+00
FA_4 0 NA_4 VI_4 1.0
GA_4 0 NA_4 a_4 ref 1.0000000000000001e-01
*
* Impinging wave, port 5
RA_5 NA_5 0 1.5811388300841898e+00
FA_5 0 NA_5 VI_5 1.0
GA_5 0 NA_5 a_5 ref 1.0000000000000001e-01
*
* Impinging wave, port 6
RA_6 NA_6 0 1.5811388300841898e+00
FA_6 0 NA_6 VI_6 1.0
GA_6 0 NA_6 a_6 ref 1.0000000000000001e-01
*
* Impinging wave, port 7
RA_7 NA_7 0 1.5811388300841898e+00
FA_7 0 NA_7 VI_7 1.0
GA_7 0 NA_7 a_7 ref 1.0000000000000001e-01
*
* Impinging wave, port 8
RA_8 NA_8 0 1.5811388300841898e+00
FA_8 0 NA_8 VI_8 1.0
GA_8 0 NA_8 a_8 ref 1.0000000000000001e-01
*
* Impinging wave, port 9
RA_9 NA_9 0 1.5811388300841898e+00
FA_9 0 NA_9 VI_9 1.0
GA_9 0 NA_9 a_9 ref 1.0000000000000001e-01
*
* Impinging wave, port 10
RA_10 NA_10 0 1.5811388300841898e+00
FA_10 0 NA_10 VI_10 1.0
GA_10 0 NA_10 a_10 ref 1.0000000000000001e-01
*
********************************


***************************************
* Synthesis of real and complex poles *
***************************************

* Real pole n. 1
CS_1 NS_1 0 9.9999999999999998e-13
RS_1 NS_1 0 1.3180381741681607e+01
GS_1_1 0 NS_1 NA_1 0 3.3859258820520427e-01
*
* Real pole n. 2
CS_2 NS_2 0 9.9999999999999998e-13
RS_2 NS_2 0 8.0897423008801013e+01
GS_2_1 0 NS_2 NA_1 0 3.3859258820520427e-01
*
* Real pole n. 3
CS_3 NS_3 0 9.9999999999999998e-13
RS_3 NS_3 0 4.1366118182514139e+04
GS_3_1 0 NS_3 NA_1 0 3.3859258820520427e-01
*
* Complex pair n. 4/5
CS_4 NS_4 0 9.9999999999999998e-13
CS_5 NS_5 0 9.9999999999999998e-13
RS_4 NS_4 0 9.4578537538487089e+03
RS_5 NS_5 0 9.4578537538487089e+03
GL_4 0 NS_4 NS_5 0 2.9057512823793905e-03
GL_5 0 NS_5 NS_4 0 -2.9057512823793905e-03
GS_4_1 0 NS_4 NA_1 0 3.3859258820520427e-01
*
* Complex pair n. 6/7
CS_6 NS_6 0 9.9999999999999998e-13
CS_7 NS_7 0 9.9999999999999998e-13
RS_6 NS_6 0 1.1227096646230913e+04
RS_7 NS_7 0 1.1227096646230912e+04
GL_6 0 NS_6 NS_7 0 2.1471771564534232e-03
GL_7 0 NS_7 NS_6 0 -2.1471771564534232e-03
GS_6_1 0 NS_6 NA_1 0 3.3859258820520427e-01
*
* Complex pair n. 8/9
CS_8 NS_8 0 9.9999999999999998e-13
CS_9 NS_9 0 9.9999999999999998e-13
RS_8 NS_8 0 1.3823412704846383e+04
RS_9 NS_9 0 1.3823412704846383e+04
GL_8 0 NS_8 NS_9 0 1.3889393831641903e-03
GL_9 0 NS_9 NS_8 0 -1.3889393831641903e-03
GS_8_1 0 NS_8 NA_1 0 3.3859258820520427e-01
*
* Real pole n. 10
CS_10 NS_10 0 9.9999999999999998e-13
RS_10 NS_10 0 1.3180381741681607e+01
GS_10_2 0 NS_10 NA_2 0 3.3859258820520427e-01
*
* Real pole n. 11
CS_11 NS_11 0 9.9999999999999998e-13
RS_11 NS_11 0 8.0897423008801013e+01
GS_11_2 0 NS_11 NA_2 0 3.3859258820520427e-01
*
* Real pole n. 12
CS_12 NS_12 0 9.9999999999999998e-13
RS_12 NS_12 0 4.1366118182514139e+04
GS_12_2 0 NS_12 NA_2 0 3.3859258820520427e-01
*
* Complex pair n. 13/14
CS_13 NS_13 0 9.9999999999999998e-13
CS_14 NS_14 0 9.9999999999999998e-13
RS_13 NS_13 0 9.4578537538487089e+03
RS_14 NS_14 0 9.4578537538487089e+03
GL_13 0 NS_13 NS_14 0 2.9057512823793905e-03
GL_14 0 NS_14 NS_13 0 -2.9057512823793905e-03
GS_13_2 0 NS_13 NA_2 0 3.3859258820520427e-01
*
* Complex pair n. 15/16
CS_15 NS_15 0 9.9999999999999998e-13
CS_16 NS_16 0 9.9999999999999998e-13
RS_15 NS_15 0 1.1227096646230913e+04
RS_16 NS_16 0 1.1227096646230912e+04
GL_15 0 NS_15 NS_16 0 2.1471771564534232e-03
GL_16 0 NS_16 NS_15 0 -2.1471771564534232e-03
GS_15_2 0 NS_15 NA_2 0 3.3859258820520427e-01
*
* Complex pair n. 17/18
CS_17 NS_17 0 9.9999999999999998e-13
CS_18 NS_18 0 9.9999999999999998e-13
RS_17 NS_17 0 1.3823412704846383e+04
RS_18 NS_18 0 1.3823412704846383e+04
GL_17 0 NS_17 NS_18 0 1.3889393831641903e-03
GL_18 0 NS_18 NS_17 0 -1.3889393831641903e-03
GS_17_2 0 NS_17 NA_2 0 3.3859258820520427e-01
*
* Real pole n. 19
CS_19 NS_19 0 9.9999999999999998e-13
RS_19 NS_19 0 1.3180381741681607e+01
GS_19_3 0 NS_19 NA_3 0 3.3859258820520427e-01
*
* Real pole n. 20
CS_20 NS_20 0 9.9999999999999998e-13
RS_20 NS_20 0 8.0897423008801013e+01
GS_20_3 0 NS_20 NA_3 0 3.3859258820520427e-01
*
* Real pole n. 21
CS_21 NS_21 0 9.9999999999999998e-13
RS_21 NS_21 0 4.1366118182514139e+04
GS_21_3 0 NS_21 NA_3 0 3.3859258820520427e-01
*
* Complex pair n. 22/23
CS_22 NS_22 0 9.9999999999999998e-13
CS_23 NS_23 0 9.9999999999999998e-13
RS_22 NS_22 0 9.4578537538487089e+03
RS_23 NS_23 0 9.4578537538487089e+03
GL_22 0 NS_22 NS_23 0 2.9057512823793905e-03
GL_23 0 NS_23 NS_22 0 -2.9057512823793905e-03
GS_22_3 0 NS_22 NA_3 0 3.3859258820520427e-01
*
* Complex pair n. 24/25
CS_24 NS_24 0 9.9999999999999998e-13
CS_25 NS_25 0 9.9999999999999998e-13
RS_24 NS_24 0 1.1227096646230913e+04
RS_25 NS_25 0 1.1227096646230912e+04
GL_24 0 NS_24 NS_25 0 2.1471771564534232e-03
GL_25 0 NS_25 NS_24 0 -2.1471771564534232e-03
GS_24_3 0 NS_24 NA_3 0 3.3859258820520427e-01
*
* Complex pair n. 26/27
CS_26 NS_26 0 9.9999999999999998e-13
CS_27 NS_27 0 9.9999999999999998e-13
RS_26 NS_26 0 1.3823412704846383e+04
RS_27 NS_27 0 1.3823412704846383e+04
GL_26 0 NS_26 NS_27 0 1.3889393831641903e-03
GL_27 0 NS_27 NS_26 0 -1.3889393831641903e-03
GS_26_3 0 NS_26 NA_3 0 3.3859258820520427e-01
*
* Real pole n. 28
CS_28 NS_28 0 9.9999999999999998e-13
RS_28 NS_28 0 1.3180381741681607e+01
GS_28_4 0 NS_28 NA_4 0 3.3859258820520427e-01
*
* Real pole n. 29
CS_29 NS_29 0 9.9999999999999998e-13
RS_29 NS_29 0 8.0897423008801013e+01
GS_29_4 0 NS_29 NA_4 0 3.3859258820520427e-01
*
* Real pole n. 30
CS_30 NS_30 0 9.9999999999999998e-13
RS_30 NS_30 0 4.1366118182514139e+04
GS_30_4 0 NS_30 NA_4 0 3.3859258820520427e-01
*
* Complex pair n. 31/32
CS_31 NS_31 0 9.9999999999999998e-13
CS_32 NS_32 0 9.9999999999999998e-13
RS_31 NS_31 0 9.4578537538487089e+03
RS_32 NS_32 0 9.4578537538487089e+03
GL_31 0 NS_31 NS_32 0 2.9057512823793905e-03
GL_32 0 NS_32 NS_31 0 -2.9057512823793905e-03
GS_31_4 0 NS_31 NA_4 0 3.3859258820520427e-01
*
* Complex pair n. 33/34
CS_33 NS_33 0 9.9999999999999998e-13
CS_34 NS_34 0 9.9999999999999998e-13
RS_33 NS_33 0 1.1227096646230913e+04
RS_34 NS_34 0 1.1227096646230912e+04
GL_33 0 NS_33 NS_34 0 2.1471771564534232e-03
GL_34 0 NS_34 NS_33 0 -2.1471771564534232e-03
GS_33_4 0 NS_33 NA_4 0 3.3859258820520427e-01
*
* Complex pair n. 35/36
CS_35 NS_35 0 9.9999999999999998e-13
CS_36 NS_36 0 9.9999999999999998e-13
RS_35 NS_35 0 1.3823412704846383e+04
RS_36 NS_36 0 1.3823412704846383e+04
GL_35 0 NS_35 NS_36 0 1.3889393831641903e-03
GL_36 0 NS_36 NS_35 0 -1.3889393831641903e-03
GS_35_4 0 NS_35 NA_4 0 3.3859258820520427e-01
*
* Real pole n. 37
CS_37 NS_37 0 9.9999999999999998e-13
RS_37 NS_37 0 1.3180381741681607e+01
GS_37_5 0 NS_37 NA_5 0 3.3859258820520427e-01
*
* Real pole n. 38
CS_38 NS_38 0 9.9999999999999998e-13
RS_38 NS_38 0 8.0897423008801013e+01
GS_38_5 0 NS_38 NA_5 0 3.3859258820520427e-01
*
* Real pole n. 39
CS_39 NS_39 0 9.9999999999999998e-13
RS_39 NS_39 0 4.1366118182514139e+04
GS_39_5 0 NS_39 NA_5 0 3.3859258820520427e-01
*
* Complex pair n. 40/41
CS_40 NS_40 0 9.9999999999999998e-13
CS_41 NS_41 0 9.9999999999999998e-13
RS_40 NS_40 0 9.4578537538487089e+03
RS_41 NS_41 0 9.4578537538487089e+03
GL_40 0 NS_40 NS_41 0 2.9057512823793905e-03
GL_41 0 NS_41 NS_40 0 -2.9057512823793905e-03
GS_40_5 0 NS_40 NA_5 0 3.3859258820520427e-01
*
* Complex pair n. 42/43
CS_42 NS_42 0 9.9999999999999998e-13
CS_43 NS_43 0 9.9999999999999998e-13
RS_42 NS_42 0 1.1227096646230913e+04
RS_43 NS_43 0 1.1227096646230912e+04
GL_42 0 NS_42 NS_43 0 2.1471771564534232e-03
GL_43 0 NS_43 NS_42 0 -2.1471771564534232e-03
GS_42_5 0 NS_42 NA_5 0 3.3859258820520427e-01
*
* Complex pair n. 44/45
CS_44 NS_44 0 9.9999999999999998e-13
CS_45 NS_45 0 9.9999999999999998e-13
RS_44 NS_44 0 1.3823412704846383e+04
RS_45 NS_45 0 1.3823412704846383e+04
GL_44 0 NS_44 NS_45 0 1.3889393831641903e-03
GL_45 0 NS_45 NS_44 0 -1.3889393831641903e-03
GS_44_5 0 NS_44 NA_5 0 3.3859258820520427e-01
*
* Real pole n. 46
CS_46 NS_46 0 9.9999999999999998e-13
RS_46 NS_46 0 1.3180381741681607e+01
GS_46_6 0 NS_46 NA_6 0 3.3859258820520427e-01
*
* Real pole n. 47
CS_47 NS_47 0 9.9999999999999998e-13
RS_47 NS_47 0 8.0897423008801013e+01
GS_47_6 0 NS_47 NA_6 0 3.3859258820520427e-01
*
* Real pole n. 48
CS_48 NS_48 0 9.9999999999999998e-13
RS_48 NS_48 0 4.1366118182514139e+04
GS_48_6 0 NS_48 NA_6 0 3.3859258820520427e-01
*
* Complex pair n. 49/50
CS_49 NS_49 0 9.9999999999999998e-13
CS_50 NS_50 0 9.9999999999999998e-13
RS_49 NS_49 0 9.4578537538487089e+03
RS_50 NS_50 0 9.4578537538487089e+03
GL_49 0 NS_49 NS_50 0 2.9057512823793905e-03
GL_50 0 NS_50 NS_49 0 -2.9057512823793905e-03
GS_49_6 0 NS_49 NA_6 0 3.3859258820520427e-01
*
* Complex pair n. 51/52
CS_51 NS_51 0 9.9999999999999998e-13
CS_52 NS_52 0 9.9999999999999998e-13
RS_51 NS_51 0 1.1227096646230913e+04
RS_52 NS_52 0 1.1227096646230912e+04
GL_51 0 NS_51 NS_52 0 2.1471771564534232e-03
GL_52 0 NS_52 NS_51 0 -2.1471771564534232e-03
GS_51_6 0 NS_51 NA_6 0 3.3859258820520427e-01
*
* Complex pair n. 53/54
CS_53 NS_53 0 9.9999999999999998e-13
CS_54 NS_54 0 9.9999999999999998e-13
RS_53 NS_53 0 1.3823412704846383e+04
RS_54 NS_54 0 1.3823412704846383e+04
GL_53 0 NS_53 NS_54 0 1.3889393831641903e-03
GL_54 0 NS_54 NS_53 0 -1.3889393831641903e-03
GS_53_6 0 NS_53 NA_6 0 3.3859258820520427e-01
*
* Real pole n. 55
CS_55 NS_55 0 9.9999999999999998e-13
RS_55 NS_55 0 1.3180381741681607e+01
GS_55_7 0 NS_55 NA_7 0 3.3859258820520427e-01
*
* Real pole n. 56
CS_56 NS_56 0 9.9999999999999998e-13
RS_56 NS_56 0 8.0897423008801013e+01
GS_56_7 0 NS_56 NA_7 0 3.3859258820520427e-01
*
* Real pole n. 57
CS_57 NS_57 0 9.9999999999999998e-13
RS_57 NS_57 0 4.1366118182514139e+04
GS_57_7 0 NS_57 NA_7 0 3.3859258820520427e-01
*
* Complex pair n. 58/59
CS_58 NS_58 0 9.9999999999999998e-13
CS_59 NS_59 0 9.9999999999999998e-13
RS_58 NS_58 0 9.4578537538487089e+03
RS_59 NS_59 0 9.4578537538487089e+03
GL_58 0 NS_58 NS_59 0 2.9057512823793905e-03
GL_59 0 NS_59 NS_58 0 -2.9057512823793905e-03
GS_58_7 0 NS_58 NA_7 0 3.3859258820520427e-01
*
* Complex pair n. 60/61
CS_60 NS_60 0 9.9999999999999998e-13
CS_61 NS_61 0 9.9999999999999998e-13
RS_60 NS_60 0 1.1227096646230913e+04
RS_61 NS_61 0 1.1227096646230912e+04
GL_60 0 NS_60 NS_61 0 2.1471771564534232e-03
GL_61 0 NS_61 NS_60 0 -2.1471771564534232e-03
GS_60_7 0 NS_60 NA_7 0 3.3859258820520427e-01
*
* Complex pair n. 62/63
CS_62 NS_62 0 9.9999999999999998e-13
CS_63 NS_63 0 9.9999999999999998e-13
RS_62 NS_62 0 1.3823412704846383e+04
RS_63 NS_63 0 1.3823412704846383e+04
GL_62 0 NS_62 NS_63 0 1.3889393831641903e-03
GL_63 0 NS_63 NS_62 0 -1.3889393831641903e-03
GS_62_7 0 NS_62 NA_7 0 3.3859258820520427e-01
*
* Real pole n. 64
CS_64 NS_64 0 9.9999999999999998e-13
RS_64 NS_64 0 1.3180381741681607e+01
GS_64_8 0 NS_64 NA_8 0 3.3859258820520427e-01
*
* Real pole n. 65
CS_65 NS_65 0 9.9999999999999998e-13
RS_65 NS_65 0 8.0897423008801013e+01
GS_65_8 0 NS_65 NA_8 0 3.3859258820520427e-01
*
* Real pole n. 66
CS_66 NS_66 0 9.9999999999999998e-13
RS_66 NS_66 0 4.1366118182514139e+04
GS_66_8 0 NS_66 NA_8 0 3.3859258820520427e-01
*
* Complex pair n. 67/68
CS_67 NS_67 0 9.9999999999999998e-13
CS_68 NS_68 0 9.9999999999999998e-13
RS_67 NS_67 0 9.4578537538487089e+03
RS_68 NS_68 0 9.4578537538487089e+03
GL_67 0 NS_67 NS_68 0 2.9057512823793905e-03
GL_68 0 NS_68 NS_67 0 -2.9057512823793905e-03
GS_67_8 0 NS_67 NA_8 0 3.3859258820520427e-01
*
* Complex pair n. 69/70
CS_69 NS_69 0 9.9999999999999998e-13
CS_70 NS_70 0 9.9999999999999998e-13
RS_69 NS_69 0 1.1227096646230913e+04
RS_70 NS_70 0 1.1227096646230912e+04
GL_69 0 NS_69 NS_70 0 2.1471771564534232e-03
GL_70 0 NS_70 NS_69 0 -2.1471771564534232e-03
GS_69_8 0 NS_69 NA_8 0 3.3859258820520427e-01
*
* Complex pair n. 71/72
CS_71 NS_71 0 9.9999999999999998e-13
CS_72 NS_72 0 9.9999999999999998e-13
RS_71 NS_71 0 1.3823412704846383e+04
RS_72 NS_72 0 1.3823412704846383e+04
GL_71 0 NS_71 NS_72 0 1.3889393831641903e-03
GL_72 0 NS_72 NS_71 0 -1.3889393831641903e-03
GS_71_8 0 NS_71 NA_8 0 3.3859258820520427e-01
*
* Real pole n. 73
CS_73 NS_73 0 9.9999999999999998e-13
RS_73 NS_73 0 1.3180381741681607e+01
GS_73_9 0 NS_73 NA_9 0 3.3859258820520427e-01
*
* Real pole n. 74
CS_74 NS_74 0 9.9999999999999998e-13
RS_74 NS_74 0 8.0897423008801013e+01
GS_74_9 0 NS_74 NA_9 0 3.3859258820520427e-01
*
* Real pole n. 75
CS_75 NS_75 0 9.9999999999999998e-13
RS_75 NS_75 0 4.1366118182514139e+04
GS_75_9 0 NS_75 NA_9 0 3.3859258820520427e-01
*
* Complex pair n. 76/77
CS_76 NS_76 0 9.9999999999999998e-13
CS_77 NS_77 0 9.9999999999999998e-13
RS_76 NS_76 0 9.4578537538487089e+03
RS_77 NS_77 0 9.4578537538487089e+03
GL_76 0 NS_76 NS_77 0 2.9057512823793905e-03
GL_77 0 NS_77 NS_76 0 -2.9057512823793905e-03
GS_76_9 0 NS_76 NA_9 0 3.3859258820520427e-01
*
* Complex pair n. 78/79
CS_78 NS_78 0 9.9999999999999998e-13
CS_79 NS_79 0 9.9999999999999998e-13
RS_78 NS_78 0 1.1227096646230913e+04
RS_79 NS_79 0 1.1227096646230912e+04
GL_78 0 NS_78 NS_79 0 2.1471771564534232e-03
GL_79 0 NS_79 NS_78 0 -2.1471771564534232e-03
GS_78_9 0 NS_78 NA_9 0 3.3859258820520427e-01
*
* Complex pair n. 80/81
CS_80 NS_80 0 9.9999999999999998e-13
CS_81 NS_81 0 9.9999999999999998e-13
RS_80 NS_80 0 1.3823412704846383e+04
RS_81 NS_81 0 1.3823412704846383e+04
GL_80 0 NS_80 NS_81 0 1.3889393831641903e-03
GL_81 0 NS_81 NS_80 0 -1.3889393831641903e-03
GS_80_9 0 NS_80 NA_9 0 3.3859258820520427e-01
*
* Real pole n. 82
CS_82 NS_82 0 9.9999999999999998e-13
RS_82 NS_82 0 1.3180381741681607e+01
GS_82_10 0 NS_82 NA_10 0 3.3859258820520427e-01
*
* Real pole n. 83
CS_83 NS_83 0 9.9999999999999998e-13
RS_83 NS_83 0 8.0897423008801013e+01
GS_83_10 0 NS_83 NA_10 0 3.3859258820520427e-01
*
* Real pole n. 84
CS_84 NS_84 0 9.9999999999999998e-13
RS_84 NS_84 0 4.1366118182514139e+04
GS_84_10 0 NS_84 NA_10 0 3.3859258820520427e-01
*
* Complex pair n. 85/86
CS_85 NS_85 0 9.9999999999999998e-13
CS_86 NS_86 0 9.9999999999999998e-13
RS_85 NS_85 0 9.4578537538487089e+03
RS_86 NS_86 0 9.4578537538487089e+03
GL_85 0 NS_85 NS_86 0 2.9057512823793905e-03
GL_86 0 NS_86 NS_85 0 -2.9057512823793905e-03
GS_85_10 0 NS_85 NA_10 0 3.3859258820520427e-01
*
* Complex pair n. 87/88
CS_87 NS_87 0 9.9999999999999998e-13
CS_88 NS_88 0 9.9999999999999998e-13
RS_87 NS_87 0 1.1227096646230913e+04
RS_88 NS_88 0 1.1227096646230912e+04
GL_87 0 NS_87 NS_88 0 2.1471771564534232e-03
GL_88 0 NS_88 NS_87 0 -2.1471771564534232e-03
GS_87_10 0 NS_87 NA_10 0 3.3859258820520427e-01
*
* Complex pair n. 89/90
CS_89 NS_89 0 9.9999999999999998e-13
CS_90 NS_90 0 9.9999999999999998e-13
RS_89 NS_89 0 1.3823412704846383e+04
RS_90 NS_90 0 1.3823412704846383e+04
GL_89 0 NS_89 NS_90 0 1.3889393831641903e-03
GL_90 0 NS_90 NS_89 0 -1.3889393831641903e-03
GS_89_10 0 NS_89 NA_10 0 3.3859258820520427e-01
*
******************************


.ends
*******************
* End of subcircuit
*******************

Note: This file as output from the automated PCB model extraction process is not formatted to be used directly in the PDN process presented here. It must first be processed using our Parse PDN Netlist tool as demonstrated in the next section.

G.4 Convert PDN Netlist to SIMPLIS and SIMetrix Compatible Netlists and Create Associated Symbol

In this exercise, you will learn how to process the Spice model, that was converted from the s-parameter data generated by a PCB layout tool, using the Parse PDN Netlist tool in the SIMetrix/SIMPLIS package.

Open schematic apps_g_1_SIMPLIS_before_opt.sxsch. The Parse PDN Netlist tool can be accessed by the Tools > Parse PDN Netlist menu item.

This tool was developed to convert CAD generated PDN Spice models into a format compatible with the SIMPLIS and SIMetrix simulators. This tool requires an PDN SPICE netlist file as input. The SIMPLIS PDN Netlist Parser, which processes these files, expects a SPICE-format description of a parasitic network, largely adhering to the SPICE-3 format but with modifications to support Laplace Transfer functions. It is specifically designed for passive linear elements and includes syntax for comments and line continuations. Upon processing the file, the tool assigns SIMPLIS-compatible node numbers, effectively bridging the differences in netlist syntax between the SPICE and SIMPLIS simulators. With a single CAD generated Spice subcircuit as input, the SIMPLIS Parse PDN Netlist tool generates an output of a single text file containing four (4) subcircuits -- two SIMPLIS subcircuits and two SIMetrix Spice subcircuits.

In addition, a SIMetrix and SIMPLIS compatible schematic symbol is automatically created. This allows for seamless integration and simulation of the PDN's impact within the SIMetrix/SIMPLIS schematic environment, providing a streamlined approach to analyze and visualize the PDN's performance and characteristics. For detailed information on the PDN parser's syntax and capabilities, refer to the comprehensive documentation, 'Acceptable Syntax for the SIMPLIS PDN Parser'.

To generate the SIMPLIS and SIMetrix compatible PDN netlist the following procedure is recommended. Open schematic apps_g_1_SIMPLIS_before_opt.sxsch in the apps_g_schematics directory.

Make sure that your simulator schematic is set to SIMPLIS mode. If it is set to SIMetrix mode, you can change it to SIMPLIS mode by selecting Simulator > Switch to SIMPLIS Mode from the menu bar.
Result: The simulator will change to SIMPLIS mode and the active simulator is visible on the bottom right of the schematic window.
Locate and click on the Parse PDN Netlist menu item by going to Tools > Parse PDN Netlist from menu bar.
Result: The Parse PDN Netlist File GUI dialog pops up.
Select the PDN netlist file PDN.cir that we will be using as the input to the PDN Netlist Parser. This SPICE model of the PCB layout was generated by IdEM. This file is located in the apps_g_schematics\Models directory.
Then Select the location and file name for the output result of this process. You should accept the recommended default filename and location for the output file.
Make sure to check the “Create symbol?” and “Create SIMetrix compatible model?” options. Then click on OK.
Result: A new window pops up which provides explanations regarding the generated PDN model and its characteristics such as including a full and a resistive-only (R_only) model. Click OK to proceed.
The next window asks if you want to 1) save the automatically created symbol to a symbol library file and install it, 2) save the symbol to the current schematic only, or 3) completely cancel the process of creating the symbol. In general, it is recommended to save the symbol to the current schematic instead of saving it in a symbol library file.
By selecting either YES or NO, the process is finalized, and a new set of instructions will appear in the command shell which you need to follow to place the PDN symbol. For purposes of this exercise, select NO because we only need to save the new symbol to the local schematic.
Result: The following message appears in the Command Shell.
Note: The next step would be to follow these instructions and place this new symbol on your VRM schematic. Then you would connect the PDN to the output inductors of your power stage, the bulk capacitors in parallel with the load, and the input terminals of your microprocessor load. To do this you would need detailed information about the PCB layout, which we are not going to address here. Instead, we will proceed with our application schematic which has already made the appropriate connections to the PDN.

Fig. G.3 shows a zoomed in portion of our application schematic apps_g_1_SIMPLIS_before_opt.sxsch where the appropriate connections to the PDN have been made. The PDN models the parasitic impedance of the PCB connections from the Power Stage to the load. The PDN also describes the parasitics associated with the connections to the many discrete bulk output capacitors in parallel with the load. Such a model also attempts to encapsulate some nuanced parasitic impedances of the layout, including trace length, width, and thickness as well as the impedances of vias that connect traces and ground planes on various layers of the PCB to one another.


	Figure G.3: Power Distribution Network (PDN), discrete bulk capacitors and microprocessor load. An ideal PDN would have zero impedance short circuits between all the pins of the PDN and an open circuit to the Reference pin.

Observe that the default mode of the PDN symbol is to point to the R_only model of the PDN. This model contains all the parasitic resistances associated with the PCB layout, but none of the reactive elements contained in the Full PDN model. The Full PDN model contains the parasitic resistive, inductive and capacitive elements of the PCB model. You can easily choose which of these two models you want to use in a particular simulation by double clicking on the PDN symbol.


	Figure G.4: By double clicking on the PDN symbol generated by the SIMPLIS PDN Parser, one can choose between the R_only model and the Full PDN model when running a simulation.

In the next exercise we will run schematic apps_g_1_SIMPLIS_before_opt.sxsch and compare the simulation results using first the R_only PDN model and then the Full PDN model.

Open schematic apps_g_1_SIMPLIS_before_opt.sxsch. Before running the simulation first verify that the PDN model is set for R_only.
Next open the F11 window of schematic apps_g_1_SIMPLIS_before_opt.sxsch and verify that there is an appropriate .include statement that will allow the SIMPLIS simulator to find the appropriate subcircuit definition of the PDN. In this case it should look like this:
because we stored the output of the PDN Netlist Parser, PDN_out.cir, in the models directory under the main schematic directory.

If you fail to provide the .include statement in the F11 window you will encounter the following error.
Press F9 to launch the simulation using the R_only PDN model. Once the simulation completes, record the CPU time required to run this simulation on your machine. You can get this information from the SIMPLIS status window.
Do NOT close your waveform viewer. We will next compare these results with those using the Full PDN model.

Double click on the PDN schematic symbol and change the model used to Full. Press F9 to run the simulation of this power system using the Full PDN model. Again, upon completion, record the CPU simulation time. Below are some reference results that illustrate the dramatic difference in simulation time depending on which of these two PDN models is used.

On a machine with an Intel Core i9 2.4GHz processor this simulation time was:

PDN Model	R_only	Full
CPU Time	51 sec	19 min

It is important to point out that one of the reasons that it is possible to run the full SIMPLIS VRM schematic with the Full PDN model in such a reasonable amount of time is that when this PDN model was extracted, it was done following the guidelines set out in the previous section. In this PDN there are 90 equivalent inductors and capacitors, the upper frequency limit for the extraction process was specified to be 500 MHz. Extracted PDNs with 1000’s of energy-storage elements would take much too long to simulate in a practical development setting.

Next, we compare the differences in the inductor current and load voltage waveforms from these two sets of results. We have already looked at portions of these two results in Fig. G.2. Here in Fig. G.5 we first observe these simulation waveforms during a 20 us window of a 530 A load pulse before zooming in on a few critical details.


	Figure G.5: In the upper grid we display the load current iLoad with the sum of three power-stage phases IL_phN and four power-stage phases IL_phS. Even under severe step loads of ~1.1 A/ns the inductor currents observed with the R_only PDN model versus the Full PDN model are within 2% of each other and the total of all the phase currents IL_Total is within ~1.3% of each other. In contrast, the difference in the input voltage to the microprocessor load VCCIN observed with these two different PDN models is much more pronounced and will be the main focus of our investigation.

Our first observation upon examining Fig. G.5 is that, whether we use the R_only PDN model or the Full PDN model, the power-stage inductor current waveforms are very close to the same. This stands to reason since the response time of the VRM control loop is considerably slower than the di/dt of the load step. This is very easy to see if we add the IL_phN and IL_pnS currents together creating IL_Total, which is the sum of all 7 power-stage inductor currents. As shown in Fig. G.2, while the di/dt of the load current is ~1.1 A/ns, the maximum di/dt of IL_Total is ~0.22 A/ns.

So, while the choice of PDN model has very little impact on the output current of the VRM, we can see that the parasitic inductance of the Full PDN model has a noticeable impact on the input voltage waveform VCCIN of the microprocessor. In Fig. G.6 we zoom into the initial current step to examine this effect in more detail.


	Figure G.6 zooms into the leading edge of a step load transient where the di/dt of the load step is approximately 1.1 A/ns. We see that the VCCIN waveform with the Full PDN model deviates most significantly from that of the R_only model during the portion of the step load when the load current has the highest di/dt slope.

We can see from Fig. G.6 that the difference in input voltage waveforms to the microprocessor VCCIN, depending on which PDN model we use, is most pronounced when the magnitude of the di/dt slope of the load current is at its maximum value. From this observation we conclude that the parasitic inductance of the PDN has a more dominant effect on the VCCIN waveform than the parasitic capacitance effects. We can observe a small second-order high frequency ringing effect due to the parasitic capacitance of the Full PDN model, but it is clear in this case that the input voltage VCCIN is dominated by the parasitic resistance and inductance of the PDB layout.

We can also conclude that for a well-designed PCB layout, much of the Power System design can be done using the R_only model of the PDN. The stability analysis and portions of the design of the control of the Power System determined by the VRM controller can all be done using the R_only model of the PDN. This is true because the VRM controller responds much slower than the voltage changes at the input to the microprocessor induced by the parasitic inductance of the PCB.

Note: This example has two attributes that reduce the detrimental impact of parasitic inductance in the PDN. First, the layout is well designed so that it inherently minimized the magnitude of the parasitic inductances introduced by the PDB layout. Second, as we noted earlier, there is a significant load line designed into the specification of this power system. This allows for more voltage swing during large step loads, thus reducing the detrimental impact of parasitic inductance.

However, how would we handle situations where one or both of these attributes are not present? How would we handle cases where the layout was not optimized for low parasitic inductance, or designs where the slope of the load line was zero? In these cases, we might suspect that perhaps the parasitic inductance of the PDN would need to be taken into account as a first order effect.

In the next section we present a method for characterizing a Full PDN and from that deriving a reduced-order PDN model that captures the main parasitic inductive effects of the Full PDN but runs much faster in the power system simulation.

G.5 Characterize PDN in SIMetrix

As discussed previously, we can readily identify situations where the R_only model of the PDN will not capture all the critical behavior of a power system during a high di/dt load transient. In these cases it will be important to capture the effects of the PCB parasitic inductance in the PDN model. However, we know that if the PDN model is too complex with too many energy-storage elements, the simulation can be impractically slow.

In the next exercise we demonstrate how to characterize the Full PDN model and compare it to the R_only model using a special purpose SIMetrix testbench circuit.

Open the testbench schematic apps_g_2_PDN_Characterization_Step1.sxsch. This schematic is set up to run in the SIMetrix Spice simulator. If your schematic is in SIMPLIS mode, switch your simulator to SIMetrix by selecting the Simulator>Switch to SIMetrix Mode menu item.
Result: The simulator will change to SIMetrix mode. The selected simulator is always visible at the bottom right of the schematic window.
Here we have two circuits, one with the R_only PDN model and one with the Full PDN model. In both cases we have all the bulk capacitors properly connected. Both circuits have an identical voltage source inputs and current sources across the output. By running this small testbench circuit in SIMetrix, we can run the Full PDN much more quickly.

Press F9 to run this simulation.


	Figure G.7: Here we see plotted a step current from 50 A to 1050 A with a constant di/dt=1 A/ns. Although the current steps for each PDN model are identical, the resulting VCCIN waveforms are quite different during the steep current step. Since this is an open loop circuit, there is no attempt to regulate the input voltage VCCIN. We can see that, for this current step, the dominant impedance of the PDN is the resistive component, although the magnitude of the voltage step due to the parasitic inductance of the Full PDN model is quite noticeable.

In the next section, we will examine the procedure for finding the optimum values for the Reduced Order PDN model shown in Fig. G.8. This will involve using the Optimiser function that was introduced to SIMetrix/SIMPLIS in version 9.0.

G.6 Create a Reduced-Order PDN model

In this section we introduce the concept of a Reduced Order PDN model which has far fewer energy-storage elements, but still does a very acceptable job of matching the performance of the Full PDN. The big advantage of the Reduced Order PDN is that it can be simulated in the full SIMPLIS schematic of Fig. G.1 in far less time than the Full PDN model. In some cases with very complex Full PDN models, the Reduced Order PDN model is the only practical way to simulate the many corner cases of a VRM design in a reasonable time frame consistent with demanding project schedules.

A Reduced Order PDN model could take a number of forms. We discuss one form and a minor variation in Section G.7. The basic form of this Reduced Order PDN is illustrated in Fig. G.8. Here we have added two inductors and one parallel resistor in series with the output of the R_only PDN model. This combination of parts is what we are calling a Reduced Order PDN. We already know that the R_only PDN model does a very good job of capturing the parasitic resistance of the PCB layout. What we will show next is that the simple addition of two inductors and one resistor in combination with the R_only PDN can in this example do a very good job of predicting the behavior of the Full PDN model.

Our procedure for creating the Reduced Order PDN is straight forward. Beginning with the SIMetrix test bench shown in Fig. G.8, we will use the built-in SIMetrix/SIMPLIS Optimiser to find an optimum set of values of the 3 additional components that combine with the R_only PDN model to form the Reduced Order PDN model. The details of this optimization process are described in detail in Appendix G.A below.

Once we have found the optimized values as shown in Appendix G.A for the Reduced Order PDN model, we will use those values to compare the Full PDN model with the Reduced Order PDN model in a SIMetrix test bench. These simulations run quite quickly making this SIMetrix test bench the best vehicle to compare the performance of these two PDN models.

G.7 Compare Performance of Full and Reduced-Order PDN models

In the next exercise we examine whether we can find a reduced-order PDN model that captures the most important inductance effects of the PDN, but with far fewer energy-storage components.

Open schematic apps_g_3_PDN_Optimization_Step2.sxsch. Observe three additional components L1, R1, and L2 that have been added to our previous testbench in series between the VCCIN pin of the R_only PDN and the Load I4. The question that we want to address is can we find values of these three components such that, when they are added to the testbench in series with the R_only PDN as shown, the resulting VCCIN_Reduced waveform closely resembles the VCCIN_Full waveform generated with the Full PDN model.


	Figure G.8 This SIMetrix testbench compares the VCCIN_Full voltage waveform with the VCCIN_Reduced voltage reform resulting from the combination of the R_only PDN model plus the additional series inductors L1 and L2 and the shunt resistor R1, which together form a Reduced Order PDN model. Following the procedure described in Appendix G.A, the values for L1, L2 and R1 have been optimized to closely match the Full PDN model using far fewer components.

Run the simulation by pressing F9. The resulting waveforms are shown below in Fig. G.9.


	Figure G.9 shows an impressive level of agreement between the VCCIN waveforms generated by the Full PDN model and the Reduced-Order PDN model.

As we can see, the VCCIN_Reduced waveform is very close to VCCIN_Full. In Fig. G.I we zoom into the two large voltage excursions in Fig. G.9 created by the large changes in slope of the load current.


Figure G.10a		Figure G.10b
	Figure G.10a and Fig. G.10b show zoomed in portions of the VCCIN waveforms of Fig. G.9. Each time there is a dramatic change in the slope of ILOAD, both when di/dt goes from 0 to 1A/ns and when di/dt goes from 1A/ns to zero, there is a corresponding jump in VCCIN. This Reduced Order model of the PDN captures quite nicely the parasitic inductance effects of the Full PDN model. However, it does not capture the high-frequency ringing behavior of VCCIN due to the interaction with the parasitic capacitances of the PCB layout.

We can see from Fig. G.10 that the Reduced Order PDN model made up of the combination of the R_only model and the three elements L1, L2 and R1 does a very nice job of modeling the inductive effects of the Full PDN model. It does not, however, attempt to model the high-frequency ringing effects due to the parasitic capacitance of the Full PDN model.

While it is not the subject of this presentation, we can point out that with the addition of one capacitor C7 and one resistor R9 to the Reduced-Order PDN model, it is possible to approximate the first half-cycle of ringing in the PDN.

In schematic apps_g_3_PDN_Optimization_Step2.sxsch locate R9 and C7 and highlight these parts. Then right click and select Enable Selected

Run the simulation by pressing F9.

Result: With the addition of one more energy-storage element, Fig. G.11 shows that we can match quite well with the Reduced Order PDN model the amplitude of the first half-cycle of high-frequency ringing of the VCCIN waveform due to the parasitic capacitance of the Full PDN model.


Figure G.11a		Figure G.11b
	Figure G.11 illustrates how with the addition of just one energy-storage element we can match the first half cycle of high-frequency ringing due to the parasitic capacitance of the PCB layout.

Whether it is worth the extra effort to try to match the first half-cycle of ringing will depend on the application. However, it is clear that being able to model the inductive effects of the PDN will be essential in many applications.

G.8 SIMPLIS Simulation Results with Optimized Reduced-Order PDN Model

In this section we implement the Reduced Order PDN in our SIMPLIS schematic and compare the step load results with both the R_only PDN model and the Full PDN model.

Open schematic apps_g_4_SIMPLIS_Final.sxsch and verify that the proper .include statement is present to pull in the PDN_out.cir model file.

This schematic is capable of producing results for multiple PDN models depending on how the schematic is configured. Here is a table that shows how to generate results for each PDN version.


	Table G.1 Parameter Configuration and CPU simulation times for SIMPLIS VRM with 4 versions of the PDN model in schematic apps_g_4_SIMPLIS_Final.sxsch.

In this exercise we generate a set of simulation results for all four PDN versions. Note that we will only output data between 203 us and 222 us. This will save some time and some disk space.

The approximate simulation time is listed for each PDN option.

Observe that unlike earlier, we Enable R10 for both Reduced Order cases. This is because it speeds up the simulation slightly and makes it easier to initialize the circuit over a wide range of load currents.

We will generate and plot the results of all four PDN models in the same order as in the Parameter Configuration Table G.1, beginning with the Full PDN model. It is important to carefully configure the schematic according to this table for each PDN model version.

Result: Figure G.12 plots the results of all four simulations using the four PDN models defined in the Configuration Table G.1. As observed earlier, except during intervals of very large values of di/dt of the load current, the R_only model predicts the behavior of the input voltage to the microprocessor quite well. Also, we will see in Figure G.13 that both Reduced Order models capture the inductive effects of the Full PDN very closely. It is also well to point out that the load current ILOAD has been created from oscilloscope data taken from lab measurements. Consequently, the step load current is more rounded and not the ideal 3-segment curve that was used in our characterization and optimization testbenches.


	Figure G.12 shows the waveforms for VCCIN, IL_phS and IL_phN using the four different PDN models listed in the above Configuration Table G.1. We see that no matter which PDN model we use the inductor currents from the Power Stage are all very close to each other. This makes sense because the Controller is not able to respond as quickly as the load current is changing. At this scale we can also observe that both Reduced Order PDN models yield results that are quite close to the Full PDN model

Figures G.13 and G.14 progressively zoom into areas of the VCCIN waveform at times of sharp di/dt transitions of the load current.


	Figure G.13 shows that both Reduced Order PDN models closely predict the behavior of VCCIN_Full.


	Figure G.14 zooms in to see the difference between VCCIN_Reduced and VCCIN_Reduced_w_Cap as compared to VCCIN_Full.

We note that the VCCIN_Reduced waveform only captures inductive behavior of the PDN, while the VCCIN_Reduced_w_cap does a reasonable job of approximating the first half cycle of high frequency ringing during a sharp change in the slope of the load current. Of course, there are limits to how well the Reduced Order PDN model can mimic the Full PDN model. The Reduced Order PDN has only two energy storage elements compared with 89 90 effective energy storage elements in the Full PDN. The Reduced Order with Capacitor PDN model adds but one capacitor to approximate this high frequency ringing. Given the 15X speed improvement of the Reduced Order models compared to the Full PDN model, this trade off appears to have some real value.

It is clear that a great deal of the power system design work can be done with one of these Reduced Order PDN models, saving a great deal of time while not sacrificing accuracy. Then, if desired, the Full PDN model could be run to verify that the critical operational requirements are met.

G.9 Summary

We have demonstrated how to take an automatically extracted Full PDN Spice model of the PCB layout parasitics and prepare that PDN model to be used in SIMetrix/SIMPLIS using the SIMPLIS PDN Parser. This tool creates an R_only resistance model and a Full PDN model that can be run in SIMetrix and SIMPLIS. We also showed how to characterize the Full PDN model in SIMetrix Spice and then obtain optimized values for a Reduced Order PDN model that adds a few components in series with the R_only model to capture the parasitic inductive behavior of the Full PDN model. These results demonstrate that the Reduced Order PDN and R_only models can be used to handle the bulk of the power system design tasks, taking advantage of their substantially faster simulation times when compared with the Full PDN model.

Appendix G.A Find Optimized values for Reduced Order PDN model

In order to find the values for the two inductors and one resistor that we will add in series with our R_only model to create our Reduced Order PDN model, we will use the Optimiser function in SIMetrix/SIMPLIS. We first must capture the waveform of the desired results, VCCIN_Full and save it to a file. This VCCIN_Full waveform will be our reference results which we will try to match with our Reduced Order PDN model.

Close schematic apps_g_3_PDN_Optimization_Step2.sxsch and DO NOT SAVE.
Open schematic apps_g_2_PDN_Characterization_Step1.sxsch. Verify that the top PDN model is set to R_only and that the lower PDN model is set to Full. Then launch a simulation by pressing F9. You should see a simulation result similar to Fig. G.7.
In the waveform viewer, select the VCCIN_Full waveform, which represents the input voltage VCCIN for the Full PDN model.
You can either copy the data to the Clipboard using the Edit>Copy ASCII Data menu item and then paste the datapoints into a text file, or directly export the data to a text file by using Edit>Export ASCII Data.
Save the waveform data to a file named VCCIN_Full.txt.
Close schematic apps_g_2_PDN_Characterization_Step1.sxsch and Do Not Save.
Open schematic apps_g_3_PDN_Optimization_Step2.sxsch. Verify that C7 and R9 from our previous exercise are Disabled. If they are not, highlight these two components and then right click on them and select the Disable Selected menu option.
Establish initial values for our 3-component Reduced Order model. In the schematic window press F11 and do the following:
- Comment out the existing “optimized” values for R1_R, L1_R, and L2_R and enable the initial values for these components.
- These initial values are provided by the user based on engineering judgement. In this case, a 1 A/ns step load would need a maximum of series inductance of 0.1 nH to achieve a voltage step of 100 mV.
Note: We have parameterized the three components L1, L2 and R1 on the schematic to accept the parameters L1_R, L2_R and R1_R. In that fashion this testbench is easily applied to a variety of application circuits.
Create an optimization with the SIMetrix/SIMPLIS Optimiser by going to File > New > Optimiser from the menu bar.
Result: The optimiser widget will appear as shown.
Press the button shown to attach the Optimiser to the target schematic.
Result: The Optimiser is now attached to the target schematic.
Next, input the parameter names and their initial values. In this application, adding reasonable minimum values may reduce the time “wasted” by the Optimiser exploring unrealistic parameter values. Recommended values for this example are provided in the F11 window as shown above.
The parameter names defined in the F11 window for this schematic are R1_R, L1_R, and L2_R.

In the Optimiser Options window, check the boxes for Show Progress Message and Write HTML Report.

A complete description of all the Optimiser Options may be found in our documentation here: Optimiser GUI Description. For a more detailed understanding of the optimizer, the reader is encouraged to check out our documentation on Optimisation and follow the examples there.

Select the algorithm that fits the target optimization. There are two optimization algorithms available. COBYLA is used when there are critical constraints on optimizer parameters or other variables from the circuit. The NELDER_MEAD algorithm is used when there are no hard constraints required by the optimization and is mostly used for curve fitting. The NELDER_MEAD algorithm is most appropriate for this application since we are curve fitting our Reduced-Order PDN model VCCIN waveform to the Full PDN model waveform.
Next, fill in the Specification View as shown below.
The Analysis window should be copy and pasted directly from the F11 window of the schematic. The same goes for the Options window. The Label is important if you have more than one analysis specified.

The Measurement definition is very important. Here we are using the CurveFit function and the two arguments are the voltage waveform for VCCIN_Full, defined by the voltage at node I3_P, and VCCIN_Reduced, defined by the voltage at node I4_P. What this function does is come up with a scalar measurement that quantifies how closely the curve I4_P fits the curve I3_P.

We are going to take this measurement from the Data of the Main simulation run (Not the DC Operating Point) and the Goal function is to minimize the difference between these two curves by varying the values of the three parameters R1_R, L1_R, and L2_R.
Once you have carefully checked your input to the Optimiser edit dialog.
Save the Optimiser to a file with the same file name as the schematic, but with the file extension of .sxopt.
Note: A properly formatted Optimiser file apps_g_3_PDN_Optimization_Step2_12.sxopt can be found in the apps_g_schematics directory
Run the Optimiser by pressing the Play button or by selecting Optimiser > Run Optimiser or by pressing F9.
You will see progress messages in the Command Shell window and a successful optimization run will result in an HTML report being displayed in the Main Window.

The optimum values will be highlighted at the bottom of the HTML report. They will also be summarized at the end of the progress reports in the Command Shell.

Note: Your optimized results are quite sensitive to your initial values, however the resulting waveforms for the Reduced Order PDN model will be very close to those shown Figures G.8 and G.9.