6.0 Customizing Testplans

DVM testplans are tab-separated text files with a .testplan extension and can be edited with either a text editor or with a spreadsheet program such as Microsoft Excel. For details on the DVM syntax, see Testplans in the DVM documentation

The following general rules apply:

• Blank lines are ignored.
• Lines starting with a asterisk (*) are considered comment lines and are ignored.
• Inline comments are not supported. You can comment out an entire line but not a single field or portion of a line.
• All non-blank, non-comment lines are interpreted as a testplan entry; that is, a test to be run.
• Testplans may include a header row. The first entry in this row must start with the following three-character sequence: *?@
• Testplans often contain symbolic values, which are either taken directly from the DVM control symbol or calculated from values taken from the DVM control symbol. By incorporating symbolic values, the same testplan can be used for a whole class of circuits, rather than for just one specific circuit.
• All entries are case insensitive.

While the number of functions and testplan entries is manageable, the syntax is exacting. Examples of the most commonly used functions are described in the following subsections:

• 6.1 Using the Var() and GlobalVar() Functions
• 6.2 Using the Change() Function

Although built-in testplans are a good place to start when creating a custom testplan, the entire syncbuck_1in_1out.testplan has 129 tests; therefore, this tutorial examines a representative sample of those 129 tests. Below is the 6.0_a_sampling_of_the_syncbuck_1in_1out.testplan, a sampling of tests from syncbuck_1in_1out.testplan. This testplan includes all nine Bode plot tests with three input voltages (nominal, minimum, and maximum) and three loads (Light, 50%, and 100%)  plus one test of each of the other test objectives.

Notes on a sampling of tests in the syncbuck_1in_1out.testplan

• The sampling-of-tests testplan includes five column headings on line #4: Analysis, Objective, Source, Load, and Label.
• Each non-comment row represents a new test (rows 6,7,8,10,11,12, etc.).
• The entries in each column (except the Label column) perform an action either before or after the simulation executes. The information in the Analysis and Objective columns is used to configure the analysis type and the actual subcircuits that are used by the functions in the Source and Load columns.
• Testplans execute from left to right and top to bottom within the limitations of the system. As an example of the limitations, if a PostProcess column was inserted into the above testplan in the first column position, the program would skip this column when configuring the schematic for simulation. The PostProcess column would be the first column executed after the simulation completes. Multiple columns of the same type are executed in the left-to-right order defined by the testplan.
• Each entry in the testplan above is a value or a function:
  • In the Analysis column, the value is Ac.
  • In the Objective column, the function StepLoad(OUTPUT:1, 50%, 100%) tells the program to set the first managed output load to a step-load subcircuit with an initial value of 50% of full load and a final value of 100% of full load. This objective also sets the analysis parameters and determines the measurements to be performed on the simulation data.
  • In the Source column, the function Source(INPUT:1, Nominal) sets the voltage of the first managed source to the nominal value set in the DVM Full Power Assist control symbol. The source subcircuit type is unchanged.
  • In the Load column, the function Load(OUTPUT:1, 50%) sets the output load to be 50% of the full load specification set in the DVM Full Power Assist control symbol. The load subcircuit type is unchanged.
  • In the Label column, the value contains a pipe "|" delimited string describing the test. This entry is not used by the program to configure the schematic or to determine what results to generate in the post processing. Instead, the label is used to populate the test selection dialog and to determine the report directory structure.

Both the abbreviated and full versions of the sync-buck testplan are available from the directory where you unzipped SIMPLIS_dvm_tutorial_examples.zip as explained in 2.0 Getting Started.

• Abbreviated testplan: testplans/6.0_a_sampling_of_the_syncbuck_1in_1out.testplan
• Full testplan: testplans/dvm_builtin-syncbuck_1in_1out.testplan