The purpose of the StepLine() test is to verify that the output voltage is within regulation when the line voltage is ramped between initial and final voltage values. The input is configured as a Ramp Input Source, and the output is configured as a Resistive Load. The initial and final voltage values are passed as arguments to the StepLine() function in the testplan. The built-in testplans support both rising and falling input voltage steps.
Both a POP and transient analysis are used in the StepLine() test.
The test report includes source and load graphs as well as the following scalar values which are defined in the Measured Scalar Values section below:
In this topic:
The StepLine() function has the following syntax with the arguments described in the table below:
StepLine(REF, START_VOLTAGE, FINAL_VOLTAGE) StepLine(REF, START_VOLTAGE, FINAL_VOLTAGE, OPTIONAL_PARAMETER_STRING)
Argument | Range | Description |
REF | n/a | The actual reference designator of the DVM Source or the generic syntax of INPUT:n where n is an integer indicating a position in the list of DVM sources. |
START_VOLTAGE | The starting source voltage. The starting voltage can be a numeric value or a symbolic value, such as "Maximum." | |
FINAL_VOLTAGE | The final source voltage. The final voltage can be a numeric value or a symbolic value, such as "Maximum." | |
OPTIONAL_PARAMETER_STRING | n/a | Parameter string with a
combination of one or more timing parameters:
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parameter_name1=parameter_value1 parameter_name2=parameter_value2The order of the parameter key-value pairs does not matter.
DVM sets the timing parameters for the StepLoad() test objective based on values that you enter on the following two tabs in the DVM Full Power Assist control symbol:
The time delay, rise time, and the simulation stop time are determined by these calculations:
\[ \text{TIME_DELAY} = \frac{\text{CYCLES_BEFORE_EVENT}}{\text{SWITCHING_FREQUENCY}} \]
\[ \text{RISE_TIME} = \frac{ abs \left( \text{FINAL_VOLTAGE}-\text{START_VOLTAGE} \right)}{\text{SLEW_RATE}} \]
\[ \text{STOP_TIME} = \text{TIME_DELAY} + \text{RISE_TIME} + \frac{\text{CYCLES_TO_RECOVER}}{\text{SWITCHING_FREQUENCY}}\]
The input voltage ramp/step timing is annotated on the graph below:
Annotation | Value |
X0 | TIME_DELAY |
X1 | TIME_DELAY + RISE_TIME |
Y0 | START_VOLTAGE |
Y1 | FINAL_VOLTAGE |
The StepLine() test objective sets the source and load subcircuits to the following:
Source | Load |
Ramp Input Source | Resistive Load |
Loads other than the output under test are set to the Resistive Load. All other sources are set to the DC Input Source.
The StepLine() test objective measures the following scalar values,where {load_name} and {src_name} are replaced by the actual load name source name:
Scalar Name | Description | ||||||||||
sw_freq | A number which represents the converter switching frequency. This scalar is generated from a fixed probe with curve label DVM Frequency. For more information, see Measuring the Switching Frequency.. | ||||||||||
vout{n}_recovery_time | The number {n}
in the scalar name is an integer indicating a position in the
list of DVM loads.
The three possible return values are the following:
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The Average, Minimum, Maximum, RMS and Peak-to-Peak values for each load voltage and current taken over the entire simulation time window. | ||||||||||
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The Average, Minimum, Maximum, RMS and Peak-to-Peak values for each source voltage and current taken over the entire simulation time window. |
In the following table, {load_name} is the name assigned to each load. The default value is LOAD. DVM forces each load name to be unique so that the scalar and specification values for each load are unique.
Scalar Name | PASS/FAIL Criteria |
Min_V{load_name} | The minimum value of the output voltage during the simulation time is greater that the minimum specification value. |
Max_V{load_name} | The maximum value of the output during the simulation time is less than the maximum specification value. |
Overshoot_V{load_name} | The maximum value of the output during the simulation time is less than the maximum overshoot specification value. |
Undershoot_V{load_name} | The minimum value of the output during the simulation time is greater than the minimum undershoot specification value. |
The StepLine() test objective is used in several built-in testplans. Shown below is a test from the DC/DC 1 input/1 output testplan. This test configures the line to step from the Minimum to Maximum symbolic values. Both values are defined on the DC Input page of the Full Power Assist DVM Control Symbol. The load is set to the Light symbolic value with a Load function.
*?@ Analysis | Objective | Source | Load | Label |
Transient | StepLine(INPUT:1, Minimum, Maximum) | Load(OUTPUT:1, Light) | Transient|Step Line|Light Load|Vin Minimum to Vin Maximum |
The following StepLine() test objective uses the OPTIONAL_PARAMETER_STRING argument to set the output load to step between the Minimum to Maximum symbolic values and sets the ramp time delay to 25us and the ramp rise time to 100us.
StepLine(INPUT:1, Minimum, Maximum, TIME_DELAY=25u RISE_TIME=100u)
You can view the complete test report in a new browser window here: StepLine() Test Report. Below is an interactive link to the same test report.