Objective

OVERWRITE_ANALYSIS

Each test objective sets a simulation analysis directive using parameters taken from the DVM Control Symbol. By specifying OVERWRITE_ANALYSIS=0, you instruct DVM to not setup an analysis directive. If you specify this parameter, you must set an analysis directive using an Analysis entry. If no analysis directive is set, the simulation will proceed using whatever analysis directives are setup for the schematic at the time the test is run. It is entirely possible that the analysis directives leftover in the schematic's F11 window from the last test are not suitable for the current test objective.

This parameter is most useful when setting up a test which modifies the default test objective behavior in some way. An example is setting up a PulseLoad() Test Objective with a repetitive pulsed load instead of the single pulse load which the objective configures by default. Clearly, the simulation stop time needs to be increased to capture a number of periods of the repetitive pulsed load. By default, the PulseLoad test objective sets up a transient analysis with a stop time equal to:

\[ \text{STOP_TIME} = \text{TIME_DELAY} + \text{RISE_TIME} + \text{PULSE_WIDTH} + \text{FALL_TIME} +  \frac{\text{CYCLES_TO_RECOVER}}{\text{SWITCHING_FREQUENCY}}\]

While you could specify each parameter in the above equation in the optional parameter string, another option is to specify OVERWRITE_ANALYSIS=0 and then use the analysis column to define the simulation analysis. In the following testplan, two tests are configured with different types of pulse load tests. The first test, on line #6, uses the DVM Control Symbol timing parameters to setup a pulse load simulation with a single pulse. The second test uses a Pulse Load - Repeating Pure Current Pulse load with a frequency 10kHz. The analysis directive set in the analysis column explicitly defines a POP and Transient analysis, with the transient analysis running to 400us. Note that the objective in this test uses the optional parameter string to pass the OVERWRITE_ANALYSIS=0 parameter/value pair. If you didn't pass this parameter, DVM would process the test from left to right as defined in the testplan. Thus, the testplan-defined analysis would be defined first, then, when the program processed the objective column, the previously configured analysis would be overwritten with the DVM Control Symbol parameters.

You can download this testplan here: overwrite_analysis.testplan This testplan runs on the "LTC3406B - DVM Advanced.sxsch" schematic taken from the DVM Tutorial. You can download the example circuits here: SIMPLIS_dvm_tutorial_examples.zip

An alternate way to setup the same test conditions is to change the order of the testplan columns. The following testplan has two electrically equivalent tests. The first test is copied from the second test in the previous testplan. The second test uses an additional analysis column to set the simulation analysis, thus reversing the order of operations. In the second test, the analysis is set after the objective, and this "last write wins" behavior means that the explicit analysis defined in the testplan is used in the simulation.

You can download this testplan here: overwrite_analysis_alternate.testplan This testplan runs on the "LTC3406B - DVM Advanced.sxsch" schematic taken from the DVM Tutorial. You can download the example circuits here: SIMPLIS_dvm_tutorial_examples.zip

RESET_TO_STEADY_STATE

During normal DVM operation, the presence of a test objective tells DVM to reset the circuit to a known state. The symbols affected by this reset operation are all Managed Sources and Loads. The program goes through this routine before the test objective is processed, allowing the test objective to "know" the circuit is in some known state before configuring the schematic.

This option should be considered a very advanced option, and no example of it's usage is given for that reason. By passing RESET_TO_STEADY_STATE=0 as part of the optional parameter string, you are telling DVM not to reset the circuit to a known state. You are then responsible for resetting the circuit to steady state yourself. One way to do this is through a LoadComponentValues testplan entry. The changes made to the sources and loads include: